09/09/2010 TDAQ WG - Louvain 1 LKr L0 trigger status report V. Bonaiuto, A. Fucci, G. Paoluzzi, A. Salamon, G. Salina, E. Santovetti, F. Sargeni, F. Scarfi’

09/09/2010 TDAQ WG - Louvain 2 L0 LKr trigger Use 2x8 or 4x4 calorimeter cells tiles New pixel based trigger processor Low granularity readout independent from the full granularity readout Fast readout after L0 for software triggers read-out boards 13k analog channels trigger sums LKr calorimeter DAQ 864 tiles L0 LKr trigger read-out after L1 L0TS read-out after L0

09/09/2010 TDAQ WG - Louvain 3 L0 Lkr trigger: architecture Concentrator TELL1: merging, sorting 8 Front-End TELL1 Front-End TELL1: pulse reconstruction (time, position and energy)‏ - 32 tiles 1 trigger sum (tile) = 2x8 or 4x4 channels 28 FE TELL1s, 7 concentrator TELL1s, 32 supercells per TELL1 1D + 1D algorithm. The calorimeter is divided in slices parallel to the x axis. In a first step (in the FE TELL1s) peaks in space and time are searched independently in each slice with a 1D algorithm along the x axis. In a second step (in the Concentrator TELL1) different peaks close in time and space are merged and assigned to the same electromagnetic cluster.

09/09/2010 TDAQ WG - Louvain 4 FE boards: pulse reconstr (time, position, energy) ‏ L0 LKr Trigger: architecture Three new mezzanines: LKr interface TX mezzanine (custom link for the trigger + ethernet for the readout) – preliminary firmware written, PCB ongoing RX mezzanine (custom link for the trigger) – tested Two 9U crates! A final TELL1 needed to reduce cables to the L0TS (1/2 cables to the L0TS) channels for the readout  864 channels (2x8 pixel supercells) for the trigger! Concentrator boards: merging, sorting TELL1 28 boards L0TS LKr interface 32 tiles TELL1 8 ch 7 boards 8 RX trig link 1-3 m copper 32 ch 2 Eth + 2 trig TX

09/09/2010 TDAQ WG - Louvain 5 TELL1 NA62 RX mezzanine (tested) Four links per mezzanine, eight links per TELL1, 1-3 meters copper up to 6.4 Gbps up to 0.6 Gbps

09/09/2010 TDAQ WG - Louvain 6 NA62 TELL1 RX mezzanine (tested)

09/09/2010 TDAQ WG - Louvain 7 NA62 TELL1 TX mezzanine 2 x gbit ethernet links -> 32 tiles x 5 samples x 16 1 MHz = 2.56 Gbps (vs 2 Gbps) 2 x Lkr trigger cables (2 x 4.8 Gbps) Mezzanine: compatible but bigger than the standard one (new fixing hole to be added on the upgraded TELL1) 1 FPGA (EP2S30F484C5N, 30k Logic Elements) Serdes for the trigger link + GBE physical interface IC TELL1 connector (32 bit TX + 32 bit RX + control signals) Preliminary firmware written PCB ongoing L0TS LKr int 8 RX trig 2 Eth 2 trig

09/09/2010 TDAQ WG - Louvain NA62 TELL1 TX mezzanine Ethernet PHY Ethernet connector Serializer FPGA Deserializer Trigger connector TELL1 connector PCB ongoing at CERN

09/09/2010 TDAQ WG - Louvain 9 Cables 3M cable suggested by National Semiconductors‏ Got from 3M the quotation for a special cable fitting our needs Minimum Order Quantity = 100 pcs of the same length Unfortunately this cable is not halogen-free as requested by CERN The problem is the individual shield. Quite easy to find an halogen free not individually shielded cable. After a long investigation two replacement found.

09/09/2010 TDAQ WG - Louvain Halogen free cameralink cable Very high quality cable, but too much expensive for our needs.

09/09/2010 TDAQ WG - Louvain 3M connectors + amphenol cable Got the quotation (3 USD / foot – minimum order quantity 2500 feet) and 10 meters sample cable. G. Paoluzzi is assembling the cable in our lab.

09/09/2010 TDAQ WG - Louvain LKr readout interface As agreed with the LKr WG a possible solution is to use high quality ethernet cables to transmit digital data. 1 tile = MHz = 640 Mbps 1 cream module = 2 tiles = 1.2 Gbps We will go on with the LKr WG toward a practical implementation but of course more investigation (and testing) is needed before committing to any solution.

09/09/2010 TDAQ WG - Louvain Hit rates (Front-End TELL1s) Instantaneous design hit rate (Marco’s TDAQ note): 30 MHz Rate in the central region (Giuseppe’s private communication): 3 times mean hit rate Clusters of 256 liquid krypton cells (conservative) All hits generate a shower (conservative) ( 30 MHz / 28 ) x 3 = 3.2 ( 30 MHz / 28 ) x 3 / 8 = 0.4 TOTAL RATE = 11 MHz vs 64 bit/cluster over 4 gbit links

09/09/2010 TDAQ WG - Louvain Hit rates (PP FPGA = ¼ TELL1) Same assumptions Fast communication between PP FPGAs in the same TELL1 -> rate reduction ( 30 MHz / 28 ) x 3 / 8 = 0.4 TOTAL RATE = 5 MHz vs 64 bit/cluster over 160 MHz ( 30 MHz / 28 ) x 3 /4 = 0.8

09/09/2010 TDAQ WG - Louvain L0 LKr Trigger output TELL1 L0TS LKr interface 32 tiles TELL1 8 ch Ricev ch link Trigger link 32 ch Eth + ch link ?????? L1 farm Readout link FE boards x28 Concentr. boards x7 1 L1 farm Readout link 2 Raw data after L0: 16 bit x 5 sampl x 32 chann x 1 MHz = 2.5 Gbps over 2 gbit eth - compression needed Reconstructed clusters after L0: 256 bit x 1 x 1 MHz = 256 Mbps