Arithmetic Intro Computer Organization 1 Computer Science Dept Va Tech February 2008 © McQuain Multiplication Design 1.0 Multiplicand Shift left 64-bit ALU Product Write Multiplier Shift right Control test 64 bits 32 bits The natural (by-hand) algorithm for integer multiplication leads to the design above. However, this requires additional 64-bit hardware for the ALU that would not be needed for implementing integer addition…

Arithmetic Intro Computer Organization 2 Computer Science Dept Va Tech February 2008 © McQuain CS 2504 The diagram at left corresponds to (and inspires) the previous design. If each step took 1 clock cycle, multiplying two 32-bit operands would take nearly 100 clock cycles. QTP: what's the cost of integer addition?

Arithmetic Intro Computer Organization 3 Computer Science Dept Va Tech February 2008 © McQuain Multiplication 2.0 Multiplicand 32-bit ALU Product Write Shift right Control test 32 bits 64 bits The revision here removes the need for a 64-bit ALU (as well as the 32-bit register for the multiplier). How does this work?

Arithmetic Intro Computer Organization 4 Computer Science Dept Va Tech February 2008 © McQuain Multiplication 2.0 The multiplier is placed in the low 32 bits of the 64-bit Product register. As the product is formed, beginning in the top half of that register, the shifting of the multipler gradually removes it "just-in-time". QTP: how does the operation count compare with the first version? 32-bit ALU Product Shift right Control test 64 bits Multiplier