1. CDA 3101 Summer 2007 Introduction to Computer Organization
Multiplication
14 June 2007

2. Multiplication More complicated than addition
Accomplished via shifting and addition
Requires more time and chip area
3 versions of pencil-and-paper algorithm
(multiplicand) __x_ (multiplier)
> copy & shift
> copy & shift
> shift
> copy & shift
Sum Partial Products

3. First Version (V.1)

4. V.1: Hardware Multiplicand (64 bits) Multiplier (32 bits) 64-bit ALU
Shift left
Multiplier (32 bits)
64-bit ALU
Shift right
Multiplier0
Product (64 bits)
Control test
Write

5. Second Version (V.2)
Product
Multiplier0

6. Final Version (V.3) M u l t i p l i c a n d 3 2 b i t s 3 2 - b i t A L U S h i f t r i g h t C o n t r o l P r o d u c t W r i t e t e s t 6 4 b i t s
Product

7. Summary Unsigned multiplication
Generate one partial product for each digit in the multiplier
Partial product =
Total product = sum of (left shifted) partial products
The multiplication of two n-bit binary integers results in a product of up to 2n bits in length
If multiplier digit = 0
Multiplicand If multiplier digit = 1

8. General View 1 2 3 4 x 1101 Multiplier (13) Product (143)
Multiplicand (11)
x Multiplier (13)
Product (143)
Multiplicand
M M0
C A Q M
Initial values
Add
32-bit ALU
Add
Shift 1 2
Shift
Shift
right
Control
Add
Shift 3
Add
Shift C
A A0
Q Q0 4
Multiplier

9. Signed Arithmetic Signed addition and subtraction
Treat operands as unsigned numbers
Use the same algorithm/hardware used for the corresponding unsigned operations
Unsigned
Signed 9 3 12 -7 3 -4
Cannot do this for multiplication!

10. Example Unsigned Signed x 1101 10001111 11 13 143 -5 -3 -113
1011 x 11 13
143 -5 -3
-113
Partial solution for negative multiplicands
(9)
x (3)
x 20
x 21
(27)
(-7)
x (3)
(-7) x 20 = (-7)
(-7) x 21 = (-14)
(-21)
No straightforward solution if multiplier is negative

11. Negative Multiplier
The bits of the multiplier no longer correspond to the partial products
Example: (-3) = 1101
The partial products would be generated based on that representation of the multiplier, i.e.:
Instead, the partial products should be generated using the following powers of 2:
1: x 20
0: x 21
1: x 22
1: x 23
- 1 x 20
- 1 x 21

12. Booth’s Algorithm A 0, Q-1 0 M Multiplicand Q Multiplier Count n START
= 10
= 01
Q0,Q-1
= 00
= 11
A A - M
A A + M
Arithmetic shift right:
A, Q, Q-1
Count Count - 1 No
Yes
Count = 0 ?
END

13. Booth’s Hardware Multiplicand M31 . . . M0 Add / Subtract 32-bit ALU
Control
SRA
A A0
Q Q0
Q-1
Multiplier

14. Example
( )
x ( )
A Q Q M
Initial values
A = A - M
Shift 1 2
Shift
A = A + M
Shift 3 4
Shift

15. Proof: Positive Multiplier
First, consider a simple positive multiplier
(one block of 1s surrounded by 0s)
M x ( ) = M x ( )
= M x ( )
= M x 30
Notice: 2n + 2n n-k = 2n+1 – 2n-k
=> M x ( ) = M x ( )
Both’s algorithm conforms to this scheme:
Subtracts when beginning of 1 block is found (1-0)
Adds when end of the block is encountered (0-1)
This scheme extends to any number of 1 blocks

16. Proof: Negative Multipliers
Representation of a negative number (X):
{ 1 xn-2 xn x1 x0 }
X = -2n-1 + xn-2*2n-2 + xn-3*2n x0*20
Assume the leftmost 0 is in the kth position
Representation of X = { … 10 Xk-1 … X0}
X = -2n-1 + 2n k+1 + xk-1*2k x0*20
-2n-1 + 2n-2 + … + 2k+1 = -2k+1
X = -2k+1 + xk-1*2k x0*20
(1-0) transition occurs and a subtraction takes place

17. MIPS Multiplication Special purpose registers for the result (Hi, Lo)
Two multiply instructions
Mult: signed
Multu: unsigned
mflo, mfhi – move contents from Hi, Lo to general purpose registers (GPRs)
No overflow detection in hardware
=> Software overflow detection
Hi must be 0 for multu or the replicated sign of Lo for mult

18. Conclusions Multiplication => Shift-and-add
Unsigned mult = Signed mult
Booth’s Algorithm used for signed mult
MIPS has special registers (Hi,Lo) and two instructions (mult, multu)
Think:
Weekend! 