1. The ARM Instruction Set
Load-Store architecture
Fixed-length (32-bit) instructions
3-operand instruction format (2 source operand regs, 1 result operand reg): ALU operations very powerful (can include shifts)
Conditional execution of ALL instructions
Load-Store multiple registers in one instruction
A single-cycle n-bit shift with ALU operation
“Combines the best of RISC with the best of CISC”

3. 4 bits to represent 15 registers

5. MAC – mUltiplier and accumulator block

7. Branching instructions
ARM instruction set
Data processing
instructions
Data transfer
Block transfer
Branching instructions
Multiply instructions
Software interrupt

8. Data Processing Instructions

9. Barrel Shifter in ARM processor is a functional unit testing that is used to perform the Shift and Rotate Operations.
Barrel Shifter provides five types of Shift and Rotate operations and they are :
Logical Shift Left (LSL)
Logical Shift Right (LSR)
Arithmetic Shift Right (ASR)
Rotate Right (ROR)
Rotate Right Extended (RRX)

10. This supports, but is not limited to:
Scaled addressing.
Multiplication by an immediate value.
Constructing immediate values.

12. LSL #5

14. LSR #5 and ASR #5

16. ROR #5 and RRX #5
RRX – rotate right extended