1. 微處理機 Microprocessor (100上) ARM 內核嵌入式SOC原理
Multiplier design 2011/10/27

2. One bit Multiplier for ARM1
Since the 32-bit addition time has a significant effect on the datapath cycle time
Maximum clock rate and the processor's performance

3. One bit Multiplier A B
Cin
Sum
Cout 1

4. B A = 1 0 0 1 * 1 1 0 1 3 2 1 0 N TURN N=0： MUL=1 A = A + (B LSL 0)
Multiplier
Shift (B)
ALU
LSL #N
A = A + 0 1
A = A + (B LSL #N)

5. Multiplier design
All ARM processors apart from the first prototype have included hardware support for integer multiplication. Two styles of multiplier have been used
Older ARM cores include low-cost multiplication hardware that supports only the 32-bit result multiply and multiply-accumulate instructions
Recent ARM cores have high-performance multiplication hardware and support the 64-bit result multiply and multiply-accumulate instructions

6. Booth algorithm Two bit multiplier
This allows all four values of the 2-bit multiplier to be implemented by a simple shift and add or subtract
x 3 =[ x (-1) + x 4 ]
carrying the x 4 over to the next cycle

7. modified Booth's algorithm
Cin
Multiplier
Shift (B)
ALU
Cout 00
LSL #2N
A = A + 0 01
A = A + (B LSL #2N) 10
LSL #(2N+1)
A = A - (B LSL #(2N+1)) 1 11
A = A - (B LSL #2N)
A = A + (B LSL #(2N+1))
A = A – (B LSL #2N)

8. B
A = *
N TURN
N=0： Cin = 0 MUL=11 A = A - (B LSL 0) set Cout = 1
A =
N=1： Cin = 1 MUL=00 A = A + (B LSL 2) set Cout = 0
A = =
N=2： Cin = 0 MUL=01 A = A + (B LSL 4) set Cout = 0
A = =
N=3： Cin = 0 MUL= A = A - (B LSL6) set Cout = 1
A = =
N=4： Cin = 1 MUL=00 A = A + (B LSL 8) set Cout = 0
A = =
Cin
Multiplier
Shift (B)
ALU
Cout 00
LSL #2N
A = A + 0 01
A = A + (B LSL #2N) 10
LSL #(2N+1)
A = A - (B LSL #(2N+1)) 1 11
A = A - (B LSL #2N)
A = A + (B LSL #(2N+1))
A = A – (B LSL #2N)

9. 實習問題
實習一: 使用One bit Multiplier將 * 的二進制乘法用組合語言寫出。
實習二: 使用Booth‘s algorithm將 * 的二進制乘法用組合語言寫出。
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