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Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: CMOS circuits,

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Presentation on theme: "Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: CMOS circuits,"— Presentation transcript:

1 http://www.eet.bme.hu Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-CMOS.ppt

2 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 2 The abstraction level of our study: SYSTEM MODULE + GATE CIRCUIT DEVICE n+ SD G V out V in

3 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 3 The CMOS inverter – recall V DD GND OUT IN n p V DD GND OUT=0 IN=1 V DD GND OUT=1 IN=0 In steady-state only on transistor is "on", the other one is always "off"

4 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 4 2 basic cases, depending on the supply voltage and threshold voltages of the transistors 1. small supply voltage: V DD < V Tn + |V Tp | only one transistor is "on" at a time 2. larger supply voltage V DD > V Tn + |V Tp | when switching over, both transistors are "on" at the same time U IN U V Tn V V Tp V DD V pMOS is "on" 0 0 nMOS is "on" pMOS is V Tp "on" nMOS is "on" Characteristic of the CMOS inverter

5 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 5 Characteristic of the CMOS inverter ► 1. small supply voltage: V DD < V Tn + |V Tp | the characteristics: = DD OUT V U < TnIN VUif............... -<< TpDDINTn VVUVifindefinit.... -< TpDDIN VVUif.......................... 0 U IN V Tn V DD -V-V Tp V DD V U OUT Indefinit V DD U IN V DD -V-V Tp V DD U OUT V Tn The middle part of the transfer characteristic is very steep, this the specific advantage of CMOS inverters.

6 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 6 ► Constructing the characteristic: Characteristic of the CMOS inverter ► 2. large supply voltage: V DD > V Tn + |V Tp | Switching over? - "mutual conduction"

7 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 7 Design for symmetrical operation: If U IN =U inv logic threshold voltage, both transistors have equal current: U GSp =V DD -U K U GSn =U K The CMOS inverter The inverter logic threshold voltage depends on the ratio of the current constants of the transistors. To have U inv at V DD /2 and V Tn =|V Tp |, then K n =K p has to be set. since hole mobility is 2... 2.5 times less The logic threshold voltage can be set by the W/L ratios 22 )()( TpinvDDpTninvn VUUKVUK  pn pnTnTpDD inv KK KKVVU U /1 /   

8 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 8 The CMOS inverter / dynamic char. ► Calculation of the switching times  What do they depend on? the current driving capability of the output the capacitive load on the output ► If the characteristics of the two transistors are exactly complementary (K n =K p and V Tn =|V Tp |), rising and falling times will be equal out

9 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 9 The capacitnces ► Intrinsic capacitances of the driving stage ► Input capacitance of the loading stage (next gate) – extrinsic or fanout capacitances ► wiring (interconnect) capacitance V out1 V in M2M2 M1M1 M4M4 M3M3 V out2 C DB2 C DB1 C GD12 intrinsic MOS transistor capacitances C G4 C G3 extrinsic MOS transistor (fanout) capacitances CwCw wiring (interconnect) capacitance

10 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 10 The capacitnces ► The intrinsic capacitances:  S-G G-D overlap capacitances  the MOS capacitance of the channel  capacitances of pn junctions ► The wiring capacitance  depends on the interconnect geometry (width, length)  with the advance of manufacturing processes this capacitance tends to increase See later

11 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 11 The CMOS inverter / dynamic char. ► Calculation of switching times  identical times, integration for the extreme values of the voltage of the load capacitance: V LM – minimal voltage of the load capacitance  If then Can be reduced by increasing the supply voltage or the W/L ratio out

12 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 12 Power consumption of CMOS inv.: ► There is no static consumption since there is no static current ► There is dynamic consumption during switching which consists of 2 parts:  Mutual conduction: During the rise of the input voltage both transistors are "on" V Tn <U IN <V DD -V Tp  Charge pumping: At switching over the output to 1 the C L loading capacitor is charged to the supply voltage through the p transistor, then it is discharged towards the ground through the n transistor. Charge is pumped from VDD to GND.

13 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 13 Power consumption of CMOS inv.: ► Mutual conduction ("short power"): During a certain period of the rise of the input signal both transistors are "on" if V Tn <U IN <V DD -V Tp this is called mutual conduction charge flowing through:, where t UD is the time while current is flowing, b is a constant depending on the signal shape. b  0.1-0.2 P ~ f V DD 3

14 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 14 Power consumption of CMOS inv.: ► Charge pumping: At switching the C L load capacitance is charged to VDD through the p-channel device when the output changes to 1, later, when switching the output to 0, it is discharged towards GND through the n-channel device. P cp =f C L V DD 2 The power consumption due to charge pumping is proportional to the frequency and the square of the supply voltage. ► Total consumption: sum of the two components (if there is mutual conduction), directly proportional to the frequency and the 2 nd and 3 rd power of the supply voltage.

15 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 15 Components of the consumption of CMOS circuits ► Dynamic components – at every switching event  mutual conduction, charge pumping  proportional to the the event density clock frequency circuit activity ► Further components due to parasitics:  subthreshold currents  leakage currents of pn junctions – nowadays already significant  leakage (tunneling) through the a gate dielectric

16 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 16 Construction ► Constructing CMOS gates ► Technology (overview of the poly-Si gate process) ► Layout

17 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 17  combination of these: complex gate CMOS gates ► Create an nMOS switching curcuit (pull down network): ► switches: nMOS transistors ► Load: the dual circuit of the nMOS network: pMOS network  series path: NAND function  paralel path: NOR function

18 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 18 ► In a CMOS inverter both transistors are actively controlled ► In case of gates there will be a PUN (pull up network: pMOS circuit) and a PDN (pull down network: nMOS circuit). The number of transistors both in PUN and PDN is equal to the number of inputs of the gate  For input combinations where the output is 0, the PDN realizes a short towards GND and the PUN is an open circuit;  if the output function is equal to 1, the PDN will be an open circuit and the PUN realizes a short towards VDD. Circuits with dual topology should be realized from n and p channel transistors ► Gates of transistors receiving the same signal are connected CMOS gates

19 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 19 CMOS gates ► NOR gate ► NAND gate For an n input CMOS gate 2n transistors are needed (passive load gates need only n+1 transistors) out

20 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 20 Construction complex CMOS gates ► dual topology (loop  cut, cut  loop) ► dual components: nMOS replaced by pMOS ► transistor gates corresponding to the same signal must be connected ► proper sizing of the W/L ratios (e/h mobility mismatch)

21 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 21 The abstraction level of our study: SYSTEM MODULE + GATE CIRCUIT DEVICE V out V in n+ SD G

22 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 22 Metal gate MOS transistor In-depth structure: Layout view: Thin oxide Drain doping Source doping Gate Drain contact Source Problems: metal gate – large V T requires accurate mask alignment

23 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 23 Poly-Si gate MOS transistor In-depth structure: Layout view: thin oxide Drain doping Source doping Gate Drain contact Source Advantages smaller V T self alignment

24 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 24 A poli-Si gate-es nMOS technológia ► Start with: p type substrate (Si wafer) cleaing, grow thick SiO 2 – this is called field oxide

25 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 25 expose to UV light through a mask, The poli-Si gate nMOS process ► Create the active zone with photolithography coat with resist, development, removal of exposed resists etching of SiO 2 removal of the resist M1: active zone

26 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 26 etch poly-Si, The poli-Si gate nMOS process ► Create the gate structure: pattern poly-Si with photolithography growth of thin oxide deposit poly-Si (resist, exposure,develop) etch thin oxide M2: poly-Si pattern

27 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 27 The poli-Si gate nMOS process ► S/D doping (implantation) the exide (thin, thick) masks the dopants this way the self-alignment of the gate is assured ► Passivation: deposit PSG

28 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 28 The poli-Si gate nMOS process ► Open contact windows through PSG photolithography (resist, etching (copy the pattern) M3: contact window pattern expose pattern,develop) cleaning

29 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 29 The poli-Si gate nMOS process ► Metallization Deposit Al photolithography, M4: metallization pattern etching, cleaning ► The recepy of the process is given, the in-depth structure is determined by the sequence of the masks ► One needs to specify the shapes on the masks  The set of shapes on subsequent masks is called layout

30 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 30 Layout of a depletion mode inverter ► Layout == set of 2D shapes on subsequent masks ► Masks are color coded:  active zone: red  poly-Si: green  contact windows:black  metal:blue ► Mask == layout layer S G D S G D Where is a transistor? Channel between two doped regions: CHANNEL = ACTIVE AND POLY

31 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 31 Layout primitives: simple shapes Gate (mask of poly-Si pattern) Contacts (window opening mask through oxide/PSG) S/D lines (mask of metallization pattern) Active zone (window opening through the oxide)

32 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 32 layout of an nMOS transistor: layout primitives on actual layers corresponding to real masks nMOS transistor layout + outline + pinsnMOS transistor macro: outline, pins, scripts: pszeudo layers nMOS D S G G Layout macros – from primitives

33 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 33 Simplified layout: stick diagram active poly metal contact Vdd Out In GND In Out W/L ratios are given 2/2

34 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 34 n+ p-Si substrate n well p+ CMOS structure (inverter)

35 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 35 Layout of a CMOS inverter p well n well

36 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 36 Layout macros – from macros and primitives nMOS D S G G pMOSDS G G Gate level layout

37 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 37 ► Further masks:  n-well (or p-well, depending on the substrate)  p doping (or n doping, depending on the substrate) ► Multiple metal layer CMOS:  each metallization needs own mask,  conatct windows, vias ► There could be multiple poly-Si layers (analog CMOS) ► Typically: 15..20 masks ► Certain rules need to be kept for manufacturability: design rules  come from the process, given by Si-foundry CMOS structures

38 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 38 Details of a CMOS circuit INV NAND3 Layout extraction: checking, real delays 2 metal layers only

39 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 39 Modern metallization

40 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 40 Intel 0.25 µm process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric

41 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 41 Si-compilers ► Logic schematic / netlist / high level description ► Transistor level schematic with W/L information ► Stick diagram layout ► Actual layout  Automatic conversion between these representations  HARDWARE SYNTHESIS 1.From behavioural description structural description 2.Implementation of the structural description with a given realization mode / manufacturing process: technology mapping We have seen basics of the realization of an application specific integrated circuit (ASIC) Designs can also be mapped to an FPGA

42 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 42 Interconnect capacitances Electrical field W H t di dielectric (SiO 2 ) substrate C pp = (  di /t di ) WL Current flow dir. Dielectric constant (SiO 2 => 3.9) L Interconnect - substrate: parallel plate capacitance

43 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 43 Interconnect capacitances C wire = C pp + C fringe + C interwire = (  di /t di )WL + (2  di )/log(t di /H) + (  di /t di )HL interwire fringe paralell plate H

44 Budapest University of Technology and Economics Department of Electron Devices 16-11-2009 CMOS circuits © András Poppe, BME-EET 2008 44 Other issues of interconnects ► Series resistance ► Distributed parameter RC line (see transmission lines) Sort of a representation of the diffusion equation

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