1. EE415 VLSI Design THE INVERTER [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

2. EE415 VLSI Design DIGITAL GATES Fundamental Parameters The key parameters that govern a digital gate’s performance and usability. l Area and Complexity l Functionality and Robustness (Reliability) l Performance »Speed (delay) »Power Consumption (dissipation) »Energy

3. EE415 VLSI Design Area and Complexity Small area very desirable for digital gate higher integration density smaller die size lower fabrication cost faster (smaller Cg) Implementation area depends on number of transistors interconnection area

4. EE415 VLSI Design Functionality and Robustness Prime requirement for digital gate: perform designed function Measured behavior deviates from expected response. Why? variations in process noise (unwanted variations of voltages and currents at the logic nodes) Logic levels V OH and V OL represent high and low logic levels difference is called the logic swing

5. EE415 VLSI Design Noise in Digital Integrated Circuits

6. EE415 VLSI Design The Voltage-Transfer Characteristic Electrical function of gate is best expressed by its voltage-transfer characteristic (VTC) (DC transfer characteristic) Plots V out = f (V in ) Gate (Switching) logic threshold voltage, V M : V M = f (V M ) intersection of VTC at V out =V in

7. EE415 VLSI Design DC Operation: Voltage Transfer Characteristic (VTC)

8. EE415 VLSI Design Mapping between analog and digital signals Problem: Output signal deviates from expected nominal value due to: noise loading of the gate output Solution: Logic levels represented by range of acceptable values Regions of acceptable values delimited by V IH and V IL represents points in VTC where (dV out /dV in ) = -1 undefined region known as transition width

9. EE415 VLSI Design Mapping between analog and digital signals

10. EE415 VLSI Design Noise Margins Measure of a gate sensitivity to noise Quantize the size of legal “0” and “1” Represents level of noise that can be tolerated when gates are cascaded NM L (noise margin low) NM L = V IL - V OL NM H (noise margin high) NM H = V OH - V IH Should be large as possible for good noise immunity

11. EE415 VLSI Design Definition of Noise Margins V IH V IL Undefined Region "1" "0" V OH V OL NM H L Gate Output Gate Input Noise Margin High Noise Margin Low

12. EE415 VLSI Design The Regenerative Property Large noise margin alone not sufficient for proper operation Gate must “boost” weak levels back to nominal values Known as regeneration (of levels) Non-regenerative gate output will converge to intermediate value Conditions for regeneration: VTC transient region gain >1 (absolute value) Gain in the two legal zones must be < 1

13. EE415 VLSI Design The Regenerative Property

14. EE415 VLSI Design Directivity A gate must be unidirectional : input not affected by output changes causes noise in input otherwise Real gate: full directivity never achievable capacitive coupling causes feedback

15. EE415 VLSI Design Fan-in and Fan-out Fan-out: Number of load gates, N, that are connected to the output of the driving gate tends to lower the logic levels deteriorates dynamic performance gate must have low output resistance to drive load library cells have maximum fan-out specification Fan-in: Number of inputs, M, to the gate large fan-in gates are more complex results in inferior static and dynamic performance

16. EE415 VLSI Design Fan-in and Fan-out

17. EE415 VLSI Design The Ideal Gate V in V out g=  R i =  R o = 0 Static CMOS comes close to ideal

18. EE415 VLSI Design VTC of Real Inverter 0.01.02.03.04.05.0 V in (V) 1.0 2.0 3.0 4.0 5.0 V o u t ( V ) V M NM H L