1. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 A few notes for your design  Finger and multiplier in schematic design  Parametric analysis  Monte-Carlo analysis

2. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 2 Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance

3. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 3

4. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 4 Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić

5. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 5 Multistage Networks Stage effort: h i = g i f i Path electrical effort: F = C out / C in Path logical effort: G = g 1 g 2 …g N Path effort: H = GF Path delay D =  d i =  p i +  h i

6. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 6 Optimum Effort per Stage When each stage bears the same effort: Minimum path delay Effective fanout of each stage: Stage efforts: g 1 f 1 = g 2 f 2 = … = g N f N

7. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 7 Example: Optimize Path g 1 = 1 g 2 = 5/3 g 3 = 5/3 g 4 = 1 Effective fanout F = 5, G = 25/9  H = GF=125/9=13.9  h=1.93 so, f 1 =h/g=1.93, f 2 =1.93*3/5=1.16, f 3 =1.16, f 4 =1.93 (note f i : effective fanout for the i th stage) a = f 1 *g 1 /g 2 =1.16 (of minimum-size 3-input NAND gate) (a*g 2 /g 1 *1=f 1 ) b = f 1 *f 2 *g 1 /g 3 = 1.34 (of minimum-size 2-input NOR gate) (b*g 3 /g 2 *a=f 2 ) c = f 1 *f 2 *f 3 *g 1 /g 4 = 2.59 (of minimum-size inverter) (c*g 4 /g 3 *b=f 3 )

8. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 8 Add Branching Effort Branching effort: A parameter used to account for how much sizing is attributed to the critical path

9. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 9 Multistage Networks Stage effort: h i = g i f i Path electrical effort: F = C out / C in Path logical effort: G = g 1 g 2 …g N Branching effort: B = b 1 b 2 …b N Path effort: H = GFB Path delay D =  d i =  p i +  h i

10. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 10 Example – 8-input AND

11. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 11 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’ best number of stages N ~ log 4 H

12. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 12 Method of Logical Effort  Compute the path effort: H = GFB  Find the best number of stages N ~ log 4 H  Compute the stage effort h = H 1/N  Sketch the path with this number of stages  Work from either end, find sizes Reference: Sutherland, Sproull, Harris, “Logical Effort”, Morgan-Kaufmann, 1999.

13. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 13 Summary

14. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 14 Power consumption of static gates  It is a strong function of transistor sizes (which affects physical capacitance), input and output rise and fall time, device thresholds, temperature and switching activity.  Switching activity is a strong function of logic function to be implemented (nature of the gate), also input signal statistics such as inter-signal dependency.  Estimate switching activity for the overall chip is a very difficult task. eg. For NOR gate, P A, P B the probabilities that input A and B stays at 1. Transition probability is then: ∂ 0->1 = [1-(1-P A )(1-P B )] (1-P A )(1-P B )

15. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 15 Complementary MOS Properties  Full rail-to-rail swing; high noise margins  Logic levels not dependent upon the relative device sizes; ratioless  Always a path to Vdd or Gnd in steady state; low output impedance  Extremely high input resistance; nearly zero steady-state input current  No direct path steady state between power and ground; no static power dissipation  Propagation delay as function of load capacitance and resistance of transistors

16. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 16 Summary: Static Complementary Gates  Static CMOS Complementary Gates is highly robust, scalable and easy to be designed.  One possible drawback is 2N number of transistors to implement an N-input logic function.  Another drawback is that parasitic capacitance is significant (driving two devices for fan-in and fan-out)  This opens the door for alternative logic design styles (either simpler or faster)

17. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 17 Ratioed Logic Static/dynamic Ratioed/ratioless Complementary/non- complementary

18. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 18 Ratioed Logic

19. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 19 Ratioed Logic In ratioed logic, the entire PUN is replaced with a single unconditional load device that pulls up the output for logic “1” Not zero!!

20. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 20 Active Loads Voltage swing now depend on the ratio of NMOS/PMOS (in contrast to ratioless complementary logic), so named ratioed

21. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 21 Pseudo-NMOS Linear region

22. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 22 Pseudo-NMOS inverter VTC Fix W/L=2 for NMOS transistor

23. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 23 Ratioed logic with better loads  It is possible to create a ratioed logic that completely eliminates static currents and provides rail-to-rail swing  Such logic combines two concepts: differential logic and positive feedback (make sure that load device is turned off when not needed)  An example of such a logic family is called DCVSL

24. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 24 Improved Loads Both the logic and its inverse are simultaneously implemented

25. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 25 DCVSL Example It is possible to share transistors among the two pull-down networks. DCVSL gives rail-to-rail swing and eliminates static power dissipation. But short-circuit power may be a problem.

26. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 26 DCVSL Transient Response 00.20.40.60.81.0 -0.5 0.5 1.5 2.5 Time [ns] V o l t a g e [V] A B A,B A,B Still ratioed since sizing of PMOS/NMOS critical to function Short-circuit path due to simultaneous on of PMOS/NMOS Delay: In->out 197ps In->out’ 321ps VS 200ps for Static MOS

27. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 27 Pass-Transistor Logic

28. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 28 Pass-Transistor Logic Allow inputs to drive source/drain terminals as well as gate terminals

29. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 29 Example: AND Gate Is B redundant? NMOS only

30. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 30 NMOS-Only Logic Unfortunately, NMOS passes strong 0 but weak 1 (the situation is even worsened by body effect) Avoid cascading multiple pass-logic without buffering!!!

31. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 31 NMOS-only Switch Though smaller voltage swing causes smaller dynamic power consumption, threshold voltage loss causes static power consumption of following inverters V B does not pull up to 2.5V, but 2.5V - V TN