1. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Topics n Logic gate delay. n Logic gate power consumption. n Driving large loads.

2. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Logic levels n Solid logic 0/1 defined by V SS /V DD. n Inner bounds of logic values V L /V H are not directly determined by circuit properties, as in some other logic families. logic 1 logic 0 unknown V DD V SS VHVH VLVL

3. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Logic level matching n Levels at output of one gate must be sufficient to drive next gate.

4. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Transfer characteristics n Transfer curve shows static input/output relationship—hold input voltage, measure output voltage.

5. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Inverter transfer curve

6. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Logic thresholds n Choose threshold voltages at points where slope of transfer curve = -1. n Inverter has a high gain between V IL and V IH points, low gain at outer regions of transfer curve. n Note that logic 0 and 1 regions are not equal sized—in this case, high pullup resistance leads to smaller logic 1 range.

7. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Noise margin n Noise margin = voltage difference between output of one gate and input of next. Noise must exceed noise margin to make second gate produce wrong output. In static gates, t=  voltages are V DD and V SS, so noise margins are V DD -V IH and V IL - V SS.

8. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Delay n Assume ideal input (step), RC load.

9. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Delay assumptions n Assume that only one transistor is on at a time. This gives two cases: –rise time, pullup on; –fall time, pullup off. n Assume resistor model for transistor. Ignores saturation region and mischaracterizes linear region, but results are acceptable.

10. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Current through transistor n Transistor starts in saturation region, then moves to linear region.

11. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Resistive model for transistor n Average V/I at two voltages: –maximum output voltage –middle of linear region n Voltage is V ds, current is given I d at that drain voltage. Step input means that V gs = V DD always.

12. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Resistive approximation

13. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Ways of measuring gate delay n Delay: time required for gate’s output to reach 50% of final value. n Transition time: time required for gate’s output to reach 10% (logic 0) or 90% (logic 1) of final value.

14. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Inverter delay circuit n Load is resistor + capacitor, driver is resistor.

15. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Inverter delay with  model  model: gate delay based on RC time constant . n V out (t) = V DD exp{-t/(R n +R L )/ C L} n t f = 2.2 R C L n For pullup time, use pullup resistance.

16. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR  model inverter delay n 90 nm process: –R n = 11.1 k  –C l = 0.12 fF n So –t f = 2.2 x 11.1E3 x 0.12E-15 = 2.9 ps.

17. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Quality of RC approximation

18. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Quality of step input approximation

19. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Results of using small pullup

20. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Other models n Current source model (used in power/delay studies): –t f = C L (V DD -V SS )/I d – = C L (V DD -V SS )/0.5 k’ (W/L) (V DD -V SS -V t ) 2 n Fitted model: fit curve to measured circuit characteristics.

21. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Body effect and gates n Difference between source and substrate voltages causes body effect. n Source for gates in middle of network may not equal substrate: 0 0 Source above VSS

22. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Body effect and gate input ordering n To minimize body effect, put early arriving signals at transistors closest to power supply: Early arriving signal

23. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Power consumption analysis n Dynamic power consumption comes from switching behavior. n Static power dissipation comes from leakage currents. n Surprising result: dynamic power consumption is independent of the sizes of the pullups and pulldowns.

24. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Power consumption circuit n Input is square wave.

25. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Power consumption n A single cycle requires one charge and one discharge of capacitor: E = C L (V DD - V SS ) 2. n Clock frequency f = 1/t. n Energy E = C L (V DD - V SS ) 2. n Power = E x f = f C L (V DD - V SS ) 2.

26. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Observations on power consumption n Resistance of pullup/pulldown drops out of energy calculation. n Power consumption depends on operating frequency. –Slower-running circuits use less power (but not less energy to perform the same computation).

27. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Speed-power product n Also known as power-delay product. n Helps measure quality of a logic family. n For static CMOS: –SP = P/f = CV 2. n Static CMOS speed-power product is independent of operating frequency. –Voltage scaling depends on this fact. –Considers only dynamic power.

28. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Sources of leakage n Weak inversion current (subthreshold current) n Gate-induced drain leakage at the gate/drain overlap. n Drain-induced barrier lowering of the source. n Punchthrough currents. n Reverse-biased pn junctions. n etc.

29. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Subthreshold leakage current n Strong function of the threshold voltage V t. n Important in 90 nm and below technologies. n Can adjust threshold by changing substrate bias. n Leakage through a chain of transistors is lower than leakage through a single transistor.

30. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Driving large loads n Sometimes, large loads must be driven: –off-chip; –long wires on-chip. n Sizing up the driver transistors only pushes back the problem—driver now presents larger capacitance to earlier stage.

31. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Cascaded driver circuit

32. FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Optimal sizing n Use a chain of inverters, each stage has transistors a larger than previous stage. n Minimize total delay through driver chain: –t tot = n(C big /C g ) 1/n t min. n Optimal number of stages: –n opt = ln(C big /C g ). Driver sizes are exponentially tapered with size ratio .