1. Functional Test of Small-Delay Faults using SAT and Craig Interpolation Presenter: Chien-Yen Kuo

2. ATPG for small delay fault Small delay fault – Assumed to be at the output of a logic gate – Small enough to be detected only with sufficiently long sensitizable path(cf. gross-delay fault) Aim to generate test sequences for these faults in sequential circuit – SATSEQ

3. SAT-based bounded model checking

4. Fixed point

5. Craig interpolation

6. Model checking flow

7. MC-instance

8. Sequence for one fault Consist of 3 sub-sequences

9. Initial state Two candidates – Synchronized state, if exist, or – Restart state (all-0 state) Synchronized sequence – Sends any state to one and the same state (synchronized state) 1 0 0 1 0 1

10. Two-pattern delay test To sensitize PO or FF to fault – Pattern 1: Control initial value at fault site – Pattern 2: Control final value and propagate fault Different in at least one PO or FF

11. Longest sensitizable path

12. Invalidation and immunity Unexpected fault propagation may invalidate the test – F-invalidation – I-invalidation – P-invalidation – I- and P-invalidation can be ruled out by sufficiently long clock period if no gross-delay fault To avoid F-invalidation (F-immune) – Enforce X (unknown) on all off-path sensitized FF

13. Fault propagation

15. Sequence connection

18. Experimental result

20. Conclusions SATSEQ, a non-scan ATPG tool for detecting small delay fault in sequential circuit – Less test length compared to scan TAT – Fully deterministic, guarantee to produce shortest possible sub-sequences