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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 201 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay tests Non-robust test Robust test Five-valued logic and test generation n Path-delay fault (PDF) and other fault models n Test application methods Combinational, enhanced-scan and normal-scan Variable-clock and rated-clock methods n At-speed test n Timing design and delay test n Summary

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 202 Delay Test Definition n A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing. n For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic. n Delay test problem for asynchronous circuits is complex and not well understood.

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 203 Digital Circuit Timing Inputs Outputs time Transient region Clock period Comb. logic Output Observation instant Input Signal changes Synchronized With clock

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 204 Circuit Delays n Switching or inertial delay is the interval between input change and output change of a gate: Depends on input capacitance, device (transistor) characteristics and output capacitance of gate. Also depends on input rise or fall times and states of other inputs (second-order effects). Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output. n Propagation or interconnect delay is the time a transition takes to travel between gates: Depends on transmission line effects (distributed R, L, C parameters, length and loading) of routing paths. Approximation: modeled as lumped delays for gate inputs. n See Section 5.3.5 for timing models.

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 205 Event Propagation Delays 2 4 6 1 1 3 5 3 1 0 0 0 2 2 Path P1 P2 P3 Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 206 Circuit Outputs n Each path can potentially produce one signal transition at the output. n The location of an output transition in time is determined by the delay of the path. Initial value Final value Clock period Fast transitions Slow transitions time

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 207 Singly-Testable Paths (Non-Robust Test) n The delay of a target path is tested if the test propagates a transition via path to a path destination. n Delay test is a combinational vector-pair, V1,V2, that: Produces a transition at path input. Produces static sensitization -- All off-path inputs assume non-controlling states in V2. V1 V2 Static sensitization guarantees a test when the target path is the only faulty path. The test is, therefore, called non-robust. It is a test with minimal restriction. A path with no such test is a false path. Target path Off-path inputs don’t care

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 208 Robust Test n A robust test guarantees the detection of a delay fault of the target path, irrespective of delay faults on other paths. n A robust test is a combinational vector-pair, V1, V2, that satisfies following conditions: n Produce real events (different steady-state values for V1 and V2) on all on-path signals. n All on-path signals must have controlling events arriving via the target path. n A robust test is also a non-robust test. n Concept of robust test is general – robust tests for other fault models can be defined.

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 209 Robust Test Conditions n Real events on target path. n Controlling events via target path. V1 V2 U1 U1/R1 S1 U0/F0 S1 U0 U0/F0 U1/R1 U0/F0 S0

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2010 A Five-Valued Algebra n Signal States: S0, U0 (F0), S1, U1 (R1), XX. n On-path signals: F0 and R1. n Off-path signals: F0=U0 and R1=U1. S0 U0 S1 U1 XX S0 S0 S0 U0 S0 U0 U0 U0 U0 S1 S0 U0 S1 U1 XX U1 S0 U0 U1 U1 XX XX S0 U0 XX XX XX Input 1 Input 2 S0 U0 S1 U1 XX S0 S0 U0 S1 U1 XX U0 U0 U0 S1 U1 XX S1 S1 S1 U1 U1 U1 S1 U1 U1 XX XX XX S1 U1 XX Input 1 Input 2 Input S0 U0 S1 U1 XX S1 U1 S0 U0 XX AND OR NOT Ref.: Lin-Reddy IEEETCAD-87

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2011 Robust Test Generation R1 S0 U0 R1 XX S0 U0 F0 U0 Path P3 Test for P3 – falling transition through path P3: Steps A through E F0 XX A. Place F0 at path origin B. Propagate F0 through OR gate; also propagates as R1 through NOT gate C. F0 interpreted as U0; propagates through AND gate D. Change off-path input to S0 to Propagate R1 through OR gate E. Set input of AND gate to S0 to justify S0 at output Robust Test: S0, F0, U0

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2012 Non-Robust Test Generation U1 U0 XX U1 U0 R1 Path P2 Fault P2 – rising transition through path P2 has no robust test. R1 XX A. Place R1 at path origin B. Propagate R1 through OR gate; interpreted as U1 on off-path signal; propagates as U0 through NOT gate D. R1 non-robustly propagates through OR gate since off- path input is not S0 C. Set input of AND gate to propagate R1 to output Non-robust test: U1, R1, U0 U1 Non-robust test requires Static sensitization: S0=U0, S1=U1 R1

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2013 Path-Delay Faults (PDF) n Two PDFs (rising and falling transitions) for each physical path. n Total number of paths is an exponential function of gates. Critical paths, identified by static timing analysis (e.g., Primetime from Synopsys), must be tested. n PDF tests are delay-independent. Robust tests are preferred, but some paths have only non-robust tests. n Three types of PDFs (Gharaybeh, et al., JETTA (11), 1997): Singly-testable PDF – has a non-robust or robust test. Multiply-testable PDF – a set of singly untestable faults that has a non-robust or robust test. Also known as functionally testable PDF. Untestable PDF – a PDF that is neither singly nor multiply testable. n A singly-testable PDF has at least one single-input change (SIC) non-robust test.

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2014 Other Delay Fault Models n Segment-delay fault -- A segment of an I/O path is assumed to have large delay such that all paths containing the segment become faulty. n Transition fault -- A segment-delay fault with segment of unit length (single gate): Two faults per gate; slow-to-rise and slow-to-fall. Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-to-rise transition fault. Models spot (or gross) delay defects. n Line-delay fault – A transition fault tested through the longest delay path. Two faults per line or gate. Tests are dependent on modeled delays of gates. n Gate-delay fault – A gate is assumed to have a delay increase of certain amount (called fault size) while all other gates retain some nominal delays. Gate-delay faults only of certain sizes may be detectable.

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2015 Slow-Clock Test Input test clock Output test clock Combinational circuit Input latches Output latches Input test clock Output test clock V1 applied V2 applied Output latched Test clock period Rated clock period

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2016 Enhanced-Scan Test Combinational circuit HL SFFHL SFF PI PO SCANIN SCAN- OUT HOLD CK TC CK: system clock TC: test control HOLD: hold signal SFF: scan flip-flop HL: hold latch CK HOLD CK period Normal mode Normal mode TC Scan mode V1 PI applied V2 PI applied Scanin V1 states Scanin V2 states V1 settles Result latched Scanout result

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2017 Normal-Scan Test Combinational circuit SFF PI PO SCANIN SCAN- OUT CK TC CK: system clock TC: test control SFF: scan flip-flop Rated CK period Normal mode TC (A) Scan mode V1 PIs applied V2 PIs applied Scanin V1 states Result latched Result scanout V2 states generated, (A) by one-bit scan shift of V1, or (B) by V1 applied in functional mode. Scan mode Normal mode TC (B) Scan mode Slow CK period t Gen. V2 states Path tested Slow clock

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2018 Variable-Clock Sequential Test T 1 PI PO T n-2 PI PO T n-1 PI PO T n+1 PI PO T n+m PI PO 1 2 1 1 2 2 T n PI PO Initialization sequence (slow clock) Path activation (rated Clock) Fault effect propagation sequence (slow clock) 0 0 1 D Off-path flip-flop Note: Slow-clock makes the circuit fault-free in the presence of delay faults.

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2019 Variable-Clock Models n Fault effect propagation can be affected by ambiguous states of off-path flip-flops at the end of the rated-clock time-frame (Chakraborty, et al., IEEETCAD, Nov. 1997): Fault model A – Off-path flip-flops assumed to be in correct states; sequential non-robust test (optimistic). Fault model B – Off-path flip-flops assumed to be in unknown state; sequential robust test (pessimistic). Fault model C – Off-path flip-flops in steady (hazard- free) state retain their correct values, while others assume unknown state; sequential robust test. n Test length: A test sequence of N vectors is repeated N times, with a different vector applied at rated-clock each time. Test time ~ N 2 x (slow-clock period)

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2020 Variable-Clock Example n ISCAS’89 benchmark s35932 (non-scan). n 2,124 vectors obtained by simulator- selection from random vectors (Parodi, et al., ITC-98). n PDF coverage, 26,228/394,282 ~ 6.7% n Longest tested PDF, 27 gates; longest path has 29 gates. n Test time ~ 4,511,376 clocks.

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2021 Rated-Clock Sequential Test n All vectors are applied with rated-clock. n Paths are singly and multiply activated potentially in several time-frames. n Test generation requires a 41-valued logic (Bose, et al., IEEETVLSI, June 1998). n Test generation is extremely complex for non- scan circuits (Bose and Agrawal, ATS-95). n Fault simulators are effective but work with conservative assumptions (Bose, et al., IEEETVLSI, Dec. 1993; Parodi, et al., ITC-98).

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2022 Comparing PDF Test Modes All PDFs of seq. circuit Combinationally testable PDFs PDFs testable by variable- clock seq. test PDFs testable by rated-clock seq. test Ref.: Majumder, et al., VLSI Design - 98

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2023 At-Speed Test n At-speed test means application of test vectors at the rated-clock speed. n Two methods of at-speed test. n External test: Vectors may test one or more functional critical (longest delay) paths and a large percentage (~100%) of transition faults. High-speed testers are expensive. n Built-in self-test (BIST): Hardware-generated random vectors applied to combinational or sequential logic. Only clock is externally supplied. Non-functional paths that are longer than the functional critical path can be activated and cause a good circuit to fail. Some circuits have initialization problem.

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2024 Timing Design & Delay Test n Timing simulation: n Critical paths are identified by static (vector-less) timing analysis tools like Primetime (Synopsys). n Timing or circuit-level simulation using designer- generated functional vectors verifies the design. n Layout optimization: Critical path data are used in placement and routing. Delay parameter extraction, timing simulation and layout are repeated for iterative improvement. n Testing: Some form of at-speed test is necessary. PDFs for critical paths and all transition faults are tested.

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Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 2025 Summary n Path-delay fault (PDF) models distributed delay defects. It verifies the timing performance of a manufactured circuit. n Transition fault models spot delay defects and is testable by modified stuck-at fault tests. n Variable-clock method can test delay faults but the test time can be long. n Critical paths of non-scan sequential circuits can be effectively tested by rated-clock tests. n Delay test methods (including BIST) for non-scan sequential circuits using slow ATE require investigation: Suppression of non-functional path activation in BIST. Difficulty of rated-clock PDF test generation. Long sequences of variable-clock tests.

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