Presentation on theme: "1 Lecture 10 Sequential Circuit ATPG Time-Frame Expansion n Problem of sequential circuit ATPG n Time-frame expansion n Nine-valued logic n ATPG implementation."— Presentation transcript:
1 Lecture 10 Sequential Circuit ATPG Time-Frame Expansion n Problem of sequential circuit ATPG n Time-frame expansion n Nine-valued logic n ATPG implementation and drivability n Complexity of ATPG n Cycle-free and cyclic circuits n Summary Original slides copyright by Mike Bushnell and Vishwani Agrawal
2 Sequential Circuits n A sequential circuit has memory in addition to combinational logic. n Test for a fault in a sequential circuit is a sequence of vectors, which n Initializes the circuit to a known state n Activates the fault, and n Propagates the fault effect to a primary output n Methods of sequential circuit ATPG n Time-frame expansion methods n Simulation-based methods
3 Example: A Serial Adder FF AnAn BnBn CnCn C n+1 SnSn s-a X X X D D Combinational logic X
4 Time-Frame Expansion AnAn BnBn FF CnCn C n+1 1 X X SnSn s-a D D Combinational logic S n-1 s-a X D D Combinational logic C n D D X A n-1 B n-1 Time-frame -1 Time-frame 0
5 Concept of Time-Frames n If the test sequence for a single stuck-at fault contains n vectors, n Replicate combinational logic block n times – Cut at flip-flops n Place fault in each block n Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Comb. block Fault Time- frame 0 Time- frame Time- frame -n+1 Unknown or given Init. state Vector 0Vector -1 Vector -n+1 PO 0 PO -1 PO -n+1 State variables Next state
6 Example FF2 FF1 A B s-a-1
7 Five-Valued Logic (Roth) 0,1, D, D, X A B X X X 0 s-a-1 D A B X X X 0 D FF1 FF2 D D Time-frame -1 Time-frame 0
8 Nine-Valued Logic (Muth) 0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X A B X X X 0 s-a-1 0/1 A B 0/X 0/1 X s-a-1 X/1 FF1 FF2 0/1 X/1 Time-frame -1 Time-frame 0
9 Implementation of ATPG n Select a PO for fault detection based on drivability analysis. n Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. n Justify the output value from PIs, considering all necessary paths and adding backward time-frames. n If justification is impossible, then use drivability to select another PO and repeat justification. n If the procedure fails for all reachable POs, then the fault is untestable. n If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, then the fault is potentially detectable.
10 Drivability Example d(0/1) = 4 d(1/0) = (CC0, CC1) = (6, 4) s-a-1 (4, 4) (10, 15) (11, 16) (10, 16) (22, 17) (17, 11) (5, 9) d(0/1) = 9 d(1/0) = d(0/1) = 109 d(1/0) = d(0/1) = 120 d(1/0) = 27 d(0/1) = d(1/0) = 32 (6, 10) FF d(0/1) = d(1/0) = 20 8 CC0 and CC1 are SCOAP combinational controllabilities d(0/1) and d(1/0) of a line are effort measures for driving a specific fault effect to that line
11 Complexity of ATPG Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock: Cycle-free circuit – No feedback among flip- flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth. Cyclic circuit – Contains feedback among flip-flops: May need 9 Nff time-frames, where Nff is the number of flip-flops. Asynchronous circuit – Higher complexity! Time- Frame 0 Time- Frame max-1 Time- Frame max-2 Time- Frame -2 Time- Frame S0S1 S2 S3 Smax max = Number of distinct vectors with 9-valued elements = 9 Nff
12 Cycle-Free Circuits n Characterized by absence of cycles among flip-flops and a sequential depth, dseq n dseq is the maximum number of flip-flops on any path between PI and PO n Both good and faulty circuits are initializable n Test sequence length for a fault is bounded by dseq + 1
13 Cycle-Free Example F1 F2 F3 Level = 1 2 F1 F2 F3 Level = dseq = 3 s - graph Circuit All faults are testable. See Example 8.6.
14 Cyclic Circuit Example F1 F2 CNT Z Modulo-3 counter s - graph F1 F2
15 Modulo-3 Counter n Cyclic structure – Sequential depth is undefined. n Circuit is not initializable. No tests can be generated for any stuck-at fault. n After expanding the circuit to 9 Nff = 81, or fewer, time-frames ATPG program calls any given target fault untestable. n Circuit can only be functionally tested by multiple observations. n Functional tests, when simulated, give no fault coverage.
16 Adding Initializing Hardware F1 F2 CNT Z Initializable modulo-3 counter s - graph F1 F2 CLR s-a-0 s-a-1 Untestable fault Potentially detectable fault
17 Benchmark Circuits Circuit PI PO FF Gates Structure Seq. depth Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s Cycle-free s Cycle-free s Cyclic s Cyclic
18 Issues n Circuits with high sequential depth are very difficult to test n Pipelined (type of cycle-free) circuits are sequential, but essentially look combinational, just with clock cycles of input-output delay - Can use combinational ATPG n Circuits with no reset state are difficult to test - Must run circuit to get to known state - Worse if cyclic circuit
19 Summary n Combinational ATPG algorithms are extended: Time-frame expansion unrolls time as combinational array Nine-valued logic system Justification via backward time n Cycle-free circuits: Require at most dseq time-frames Always initializable n Cyclic circuits: May need 9 Nff time-frames Circuit must be initializable Full or partial scan can make circuit cycle-free
20 Practical Testing n Only small sequential circuits can be tested - Fault coverage often low - ATPG time too high n Use mostly-full scan to minimize number of unscanned flip-flops n Initialize most unscanned flip-flops n Main source of X values are “blackbox” memories - “Blackbox” means ATPG does not see inside module - Cannot make these X’s go away