1. 10/23: Lecture Topics Input/Output –Mouse, Disk and Network –Buses –SCSI Midterm review

2. Mouse Interfaces Pointing device must provide: –Status of each button –Rate of motion in X and Y directions Software must interpret the input –Double clicks –Limits to motion, speed Grid lines Rate of motion Screen position Mouse interface Device driver

3. Disk Interface Only two operations on a disk: –read block, write block Hidden behind the interface: –block  sector mappings –maybe multiple sectors per block –maybe some blocks have gone bad Unknown to the disk: –contents of the blocks/sectors Sectors Blocks Files Disk interface File system interface

4. Networks The device that lets a system connect to a network: network interface card Listens for data on the network important to this system Bundles the bits into packets and signals the OS when a packet is complete Also takes packets from OS and sends them as bits on the wire

5. Networking Interfaces OS puts extra packets in to define where stream begins and ends NIC puts extra bits in to define where packets begin and end Bits Packets Streams NIC interface Networking protocols

6. Network Example GET http://cnn.com/index.html YOU CNN GET http://cnn.com/index.html From: YOU To: CNN GET http://cnn.com/index.html From: YOU To: CNN STREAMS PACKETS Internet 1010111101010100110101010101010111 10101111010101001 BITS

7. YOUCNN STREAMS PACKETS Internet 1010111101010100110101010101010111 10101111010101001 Part 1 From: CNN To: YOU Part 2 From: CNN To: YOU Part 3 From: CNN To: YOU Part 4 From: CNN To: YOU Part 1 From: CNN To: YOU Part 2 From: CNN To: YOU Part 3 From: CNN To: YOU Part 4 From: CNN To: YOU BITS

8. Communicating with Devices the chip system bus level 2 cache main memory input/ output level 1 cache registers functional units control PC

9. System Bus Lots of variations: –How many bits can be sent simultaneously (bus width)? –How will access to the bus be controlled? –Synchronous (clocked) vs. asynchronous (handshake protocol)

10. Commands to I/O Devices Memory-mapped I/O –A special region of memory is set aside for a device –Loads and stores to addresses in this region are interpreted as commands to the device –Provides easy access control via the memory system Special I/O instructions

11. Device to Processor Comm. The device has some information for the processor. Two ways to convey it: –Issue an interrupt –Wait for the processor to ask for it - polling Which is better, interrupt-driven I/O or polling? Depends on: –time sensitivity of data –whether data is expected

12. Device to Memory Comm. Direct Memory Access (DMA) allows devices and memory to communicate without involvement of processor Processor sets up the transaction Device and memory transfer the data Device interrupts processor to signal completion The processor gets a lot of other work done while transfer is happening

13. Performance Issues in I/O Processors double in speed every 18 months Networks double in speed more slowly, perhaps every 3 years Disks improve very slowly, because they are limited by mechanical factors

14. The I/O Bottleneck System A: processor speed = 100 MHz; disk transfer takes 10 ms –How many clock cycles elapse while disk transfer takes place? System B: processor speed = 400 MHz; disk transfer still takes 10 ms –How many clock cycles now?

15. SCSI vs. IDE SCSI devices share one controller Each IDE device has its own controller SCSI is not inherently faster than IDE –in the past, high performance disks were only available with SCSI interfaces –now, high and low performance disks are available with either IDE or SCSI SCSI supports disconnect –a device doesn’t hold on to the bus while servicing a request Firewire is SCSI but even faster

16. Midterm Review Pipelining (25) Caches (20) Assembly language (20) Procedure call (13) ISA, Compiling/Linking/Loading etc. (10) I/O (6) 2’s complement/floating point/base conversions (6)

17. Assembly Language Architecture vs. Organization Machine language is the sequence of 1’s and 0’s that the CPU executes Assembly is an ascii representation of machine language A long long time ago, everybody programmed assembly Programmers that interface with the raw machine still use it –compiler/OS writers, hardware manufacturers Other programmers still need to know it –understand how the OS works –understand how to write efficient code

18. Instructions to Know lw, sw, add, addi, sub, beq, bne, bgt, blt, slt, slti, move, jal, jr, j Know what each of these instruction does Know which instruction format is used by each instruction

19. MIPS Instructions and Addressing Types of MIPS instructions –arithmetic operations (add, addi, sub) operands must be registers or immediates –memory operations lw/sw, lb/sb etc., only operations to access memory address is a register value + an immediate –branch instructions conditional branch (beq, bne) unconditional branch (j, jal, jr) MIPS addressing modes, –register, displacement, immediate, pc-relative, pseudodirect

20. Accessing Memory Memory is a big array of bytes and the address is the index Addresses are 32-bits (an address is the same as a pointer) A word is 4 bytes Accesses must be aligned

21. Representing Numbers Bits have no inherent meaning Conversion between decimal, binary and hex 2’s complement representation for signed numbers –makes adding signed and unsigned easy –flip the bits and add 1 to convert +/- floating point representation –sign bit, exponent (w/ bias), and significand (leading 1 assumed)

22. Instruction Formats The opcode (1 st six bits of instruction) determines which format to use R (register format) –add $r0, $r1, $r2 –[op, rs, rt, rd, shamt, func] I (immediate format) –lw $r0, 16($t0) –addi $r0, $t1, -14 –[op, rs, rt, 16-bit immediate] J (jump format) –jal ProcedureFoo –[op, address]

23. MIPS Registers Integer registers hold 32-bit values –integers, addresses Purposes of the different registers –$s0-$s7 –$t0-$t9 –$a0-$a3 –$v0-$v1 –$sp, $fp –$ra –$zero –$at

24. Procedure Calls Calling the procedure is a jump to the label of the procedure –“jal ProcedureName” what happens? Returning from a procedure is a jump to the instruction after “jal ProcedureName” –“jr $ra” Arguments are passed in $a0-$a3 Return values are passed back in $v0-$v1 $t0-$t9 and the stack is used for local variables Registers are saved on the stack, but not automatically –if necessary, caller saves $t0-$t9, $a0-$a3, $ra –if necessary, callee saves $s0-$s7

25. Preservation Conventions Preserved (Callee saved) Not Preserved (Caller saved) Saved registers: $s0- $s7 Stack pointer register: $sp Frame pointer register: $fp Return address register: $ra Temporary registers: $t0-$t9 Argument registers: $a0-$a3 Return value registers: $v0-$v1

26. Understanding Assembly Understand the subset of assembly that we’ve used, know what the instructions do Trace through assembly language snippets Assembly  C, recognize –while loops, if statements, procedure calls C  Assembly, convert –while loops, if statements, procedure calls

27. Pipelining What happens in each execution stage –IF, ID, MEM, EX, WB Concept of pipelining Latency vs. throughput Speedup Dependencies vs. hazards Data Hazards –stall –forwarding

28. Pipelining Cont’ Control Hazards –stall –move branch hardware to ID stage –branch delay slot –static and dynamic branch prediction

29. Caches Memory hierarchy Spatial and temporal locality Where can a block be placed? –Direct mapped, Set/Fully associative Partition an address into tag, index and block offset based on cache parameters What happens on a write access? –Write-back or Write-through Which block should be replaced? –Random or LRU (Least Recently Used) What kinds of misses? –compulsory, capacity conflict

30. I/O Disk layout Components of disk latency