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Advanced Computer Architecture 5MD00 / 5Z033 MIPS Instruction-Set Architecture Henk Corporaal TUEindhoven 2011.

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Presentation on theme: "Advanced Computer Architecture 5MD00 / 5Z033 MIPS Instruction-Set Architecture Henk Corporaal TUEindhoven 2011."— Presentation transcript:

1 Advanced Computer Architecture 5MD00 / 5Z033 MIPS Instruction-Set Architecture Henk Corporaal TUEindhoven 2011

2 H.Corporaal 5MD002 Topics n Instructions & MIPS instruction set n Where are the operands ? n Machine language n Assembler n Translating C statements into Assembler n For details see the book (ch 2):

3 H.Corporaal 5MD003 Main Types of Instructions n Arithmetic u Integer u Floating Point n Memory access instructions u Load & Store n Control flow u Jump u Conditional Branch u Call & Return

4 H.Corporaal 5MD004 MIPS arithmetic n Most instructions have 3 operands Operand order is fixed (destination first) Example: C code: A = B + C MIPS code: add $s0, $s1, $s2 ($s0, $s1 and $s2 are associated with variables by compiler)

5 H.Corporaal 5MD005 MIPS arithmetic C code: A = B + C + D; E = F - A; MIPS code: add $t0, $s1, $s2 add $s0, $t0, $s3 sub $s4, $s5, $s0 n Operands must be registers, only 32 registers provided n Design Principle: smaller is faster. Why?

6 H.Corporaal 5MD006 Registers vs. Memory n Arithmetic instruction operands must be registers, — only 32 registers provided n Compiler associates variables with registers n What about programs with lots of variables ? CPU Memory IO register file

7 H.Corporaal 5MD007 Register allocation n Compiler tries to keep as many variables in registers as possible n Some variables can not be allocated u large arrays (too few registers) u aliased variables (variables accessible through pointers in C) u dynamic allocated variables F heap F stack n Compiler may run out of registers => spilling

8 H.Corporaal 5MD008 Memory Organization n Viewed as a large, single-dimension array, with an address n A memory address is an index into the array n "Byte addressing" means that successive addresses are one byte apart 0 1 2 3 4 5 6... 8 bits of data

9 H.Corporaal 5MD009 Memory Organization n Bytes are nice, but most data items use larger "words" n For MIPS, a word is 32 bits or 4 bytes. n 2 32 bytes with byte addresses from 0 to 2 32 -1 n 2 30 words with byte addresses 0, 4, 8,... 2 32 -4... 0 4 8 12 32 bits of data Registers hold 32 bits of data

10 H.Corporaal 5MD0010 Memory layout: Alignment Words are aligned n What are the least 2 significant bits of a word address? this word is aligned; the others are not! address 0 4 8 12 16 20 24 31071523

11 H.Corporaal 5MD0011 Instructions: load and store Example: C code: A[8] = h + A[8]; MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 32($s3) n Store word operation has no destination (reg) operand n Remember arithmetic operands are registers, not memory!

12 H.Corporaal 5MD0012 Our First C code translated n Can we figure out the code? swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } swap: muli $2, $5, 4 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 Explanation: index k : $5 base address of v: $4 address of v[k] is $4 + 4.$5

13 H.Corporaal 5MD0013 So far we’ve learned: n MIPS — loading words but addressing bytes — arithmetic on registers only Instruction Meaning add $s1, $s2, $s3 $s1 = $s2 + $s3 sub $s1, $s2, $s3 $s1 = $s2 – $s3 lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1

14 H.Corporaal 5MD0014 n Instructions, like registers and words of data, are also 32 bits long  Example: add $t0, $s1, $s2  Registers have numbers: $t0=9, $s1=17, $s2=18 n Instruction Format: Machine Language: R-type instr Can you guess what the field names stand for? 6 bits 5 bits 6 bits5 bits 000000 10001 10010 0100000000 100000 op rs rt rd shamt funct

15 H.Corporaal 5MD0015 n Consider the load-word and store-word instructions, u What would the regularity principle have us do? u New principle: Good design demands a compromise n Introduce a new type of instruction format u I-type for data transfer instructions u other format was R-type for register Example: lw $t0, 32($s2) 35 18 9 32 op rs rt 16 bit number Machine Language: I-type instr

16 H.Corporaal 5MD0016 n Decision making instructions u alter the control flow, u i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label Example: if (i==j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label:.... Control

17 H.Corporaal 5MD0017 MIPS unconditional branch instructions: j label Example: if (i!=j) beq $s4, $s5, Lab1 h=i+j; add $s3, $s4, $s5 else j Lab2 h=i-j;Lab1:sub $s3, $s4, $s5 Lab2:... n Can you build a simple for loop? Control

18 H.Corporaal 5MD0018 So far (including J-type instr): n Instruction Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 – $s3 lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1 bne $s4,$s5,L Next instr. is at Label if $s4 ° $s5 beq $s4,$s5,L Next instr. is at Label if $s4 = $s5 j Label Next instr. is at Label n Formats: op rs rt rdshamtfunct op rs rt 16 bit address op 26 bit address RIJRIJ

19 H.Corporaal 5MD0019 n We have: beq, bne, what about Branch-if-less-than? New instruction: meaning: if $s1 < $s2 then $t0 = 1 slt $t0, $s1, $s2 else $t0 = 0 Can use this instruction to build " blt $s1, $s2, Label " — can now build general control structures n Note that the assembler needs a register to do this, — use conventions for registers Control Flow

20 H.Corporaal 5MD0020 Used MIPS compiler conventions

21 H.Corporaal 5MD0021 n Small constants are used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18; MIPS Instructions: addi $29, $29, 4 slti $8, $18, 10 andi $29, $29, 6 ori $29, $29, 4 Small Constants: immediates

22 H.Corporaal 5MD0022 n We'd like to be able to load a 32 bit constant into a register Must use two instructions; new "load upper immediate" instruction lui $t0, 1010101010101010 10101010101010100000000000000000 1010101010101010 ori 10101010101010100000000000000000 filled with zeros How about larger constants? Then must get the lower order bits right, i.e., ori $t0, $t0, 1010101010101010

23 H.Corporaal 5MD0023 n Assembly provides convenient symbolic representation u much easier than writing down numbers u e.g., destination first n Machine language is the underlying reality u e.g., destination is no longer first n Assembly can provide 'pseudoinstructions'  e.g., “ move $t0, $t1 ” exists only in Assembly  would be implemented using “ add $t0,$t1,$zero ” n When considering performance you should count real instructions Assembly Language vs. Machine Language

24 H.Corporaal 5MD0024 n Instructions: bne $t4,$t5,Label Next instruction is at Label if $t4  $t5 beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5 j Label Next instruction is at Label n Formats: n Addresses are not 32 bits — How do we handle this with load and store instructions? op rs rt 16 bit address op 26 bit address IJIJ Addresses in Branches and Jumps

25 H.Corporaal 5MD0025 n Instructions: bne $t4,$t5,Label Next instruction is at Label if $t4  $t5 beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5 n Formats: use I-type n Could specify a register (like lw and sw) and add it to address u use Instruction Address Register (PC = program counter) u most branches are local (principle of locality) n Jump instructions just use high order bits of PC u address boundaries of 256 MB op rs rt 16 bit address I Addresses in Branches

26 H.Corporaal 5MD0026 To summarize:

27 H.Corporaal 5MD0027 To summarize:

28 H.Corporaal 5MD0028 MIPS (3+2) addressing modes overview

29 H.Corporaal 5MD0029 Intermezzo: another approach 80x86 see intel museum: n 1978: The Intel 8086 is announced (16 bit architecture) n 1980: The 8087 floating point coprocessor is added n 1982: The 80286 increases address space to 24 bits, +instructions n 1985: The 80386 extends to 32 bits, new addressing modes n 1989-1995: The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance) n 1997: Pentium II with MMX is added n 1999: Pentium III, with 70 more SIMD instructions n 2001: Pentium IV, very deep pipeline (20 stages) results in high freq. n 2003: Pentium IV – Hyperthreading n 2005: Multi-core solutions n 2008: Low power ATOM: about 1 Watt n 2009: Lincroft: integrated graphics Note: AMD has competitive processors

30 H.Corporaal 5MD0030 A dominant architecture: 80x86 n See your textbook for a more detailed description n Complexity: u Instructions from 1 to 17 bytes long u one operand must act as both a source and destination u one operand can come from memory u complex addressing modes e.g., “base or scaled index with 8 or 32 bit displacement” n Saving grace: u the most frequently used instructions are not too difficult to build u compilers avoid the portions of the architecture that are slow

31 H.Corporaal 5MD0031 Starting a program n Compile and Assemble C program n Link u insert library code u determine addresses of data and instruction labels u relocation: patch addresses n Load into memory u load text (code) u load data (global data)  initialize $sp, $gp u copy parameters to the main program onto the stack u jump to ‘start-up’ routine  copies parameters into $ai registers F call main

32 H.Corporaal 5MD0032 Starting a program C program compiler Assembly program assembler Object program (user module)Object programs (library) linker Executable loader Memory

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