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REALITY STATISTICAL CHARACTERIZATION OF A HIGH-K METAL GATE 32NM ARM926 CORE UNDER PROCESS VARIABILITY IMPACT Paul Zuber Petr Dobrovolny Miguel Miranda.

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Presentation on theme: "REALITY STATISTICAL CHARACTERIZATION OF A HIGH-K METAL GATE 32NM ARM926 CORE UNDER PROCESS VARIABILITY IMPACT Paul Zuber Petr Dobrovolny Miguel Miranda."— Presentation transcript:

1 REALITY STATISTICAL CHARACTERIZATION OF A HIGH-K METAL GATE 32NM ARM926 CORE UNDER PROCESS VARIABILITY IMPACT Paul Zuber Petr Dobrovolny Miguel Miranda Imec, Process Technologies Unit, Design & Technology Enablement Group, INSITE Kapeldreef 75, B-3001 Leuven, Belgium Firstname.Lastname@imec.be Selma Laabidi Virgile Javerliac Yves Laplanche ARM, Physical IP Division (PIPD), R&D group 60 Rue des Berges, F-38000 Grenoble, France Firstname.Lastname@arm.com

2 MEMORIES AND SSTA Local (Intra-die) Critical Path Delay Breakdown in ARM 926 14% of clock period margin for intra-die variability: 2 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

3 MEMORIES AND SSTA Local (Intra-die) Critical Path Delay Breakdown in ARM 926 SRAM 14% of clock period margin for intra-die variability: 2 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

4 MEMORIES AND SSTA SRAM variability dominates total intra-die variation by 75% Yet, no approach can give a SSTA view on memories. ▸ In this work, we quantify that memory contribution on an ARM926 core Local (Intra-die) Critical Path Delay Breakdown in ARM 926 SRAM 14% of clock period margin for intra-die variability: 2 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

5 MOTIVATION / OBJECTIVES Challenge: ▸ Today’s deep submicron technologies suffer from variability ▸ High-k / Metal Gate promising technology solution Problem: ▸ Assessment of process variability on product level difficult ▸ Memories play important role ▸ Commercial solutions to capture memory variability incomplete => Incomplete SSTA analysis Objectives: ▸ Correctly characterize memory’s statistical contribution ▸ Quantify variability’s impact of an ARM core timing including all 20+ memories 3 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

6 MOTIVATION / OBJECTIVES Challenge: ▸ Today’s deep submicron technologies suffer from variability ▸ High-k / Metal Gate promising technology solution Problem: ▸ Assessment of process variability on product level is difficult ▸ Memories play important role ▸ Commercial solutions to capture memory variability are incomplete → Incomplete SSTA analysis Objectives: ▸ Correctly characterize memory’s statistical contribution ▸ Quantify variability’s impact of an ARM core timing including all 20+ memories 3 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

7 MOTIVATION / OBJECTIVES Challenge: ▸ Today’s deep submicron technologies suffer from variability ▸ High-k / Metal Gate promising technology solution Problem: ▸ Assessment of process variability on product level is difficult ▸ Memories play important role ▸ Commercial solutions to capture memory variability are incomplete → Incomplete SSTA analysis Objectives: ▸ Correctly characterize memory’s statistical contribution ▸ Quantify variability’s impact of an ARM core timing including all 20+ memories 3 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

8 ALTERNATIVES FOR DEALING WITH MEMORY BLOCKS FOR STATISTICAL CORE CHARACTERIZATION 4 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

9 ALTERNATIVES FOR DEALING WITH MEMORY BLOCKS FOR STATISTICAL CORE CHARACTERIZATION.lib 4 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

10 ALTERNATIVES FOR DEALING WITH MEMORY BLOCKS FOR STATISTICAL CORE CHARACTERIZATION Use of corners = No benefits of SSTA (as we will see).lib 4 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

11 ALTERNATIVES FOR DEALING WITH MEMORY BLOCKS FOR STATISTICAL CORE CHARACTERIZATION Use of corners = No benefits of SSTA (as we will see) Statistical simulation of entire SRAM impossible unless we have 100 days characterization time.lib 4 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

12 ALTERNATIVES FOR DEALING WITH MEMORY BLOCKS FOR STATISTICAL CORE CHARACTERIZATION Use of corners = No benefits of SSTA (as we will see) Statistical simulation of entire SRAM impossible unless we have 100 days characterization time Considering single memory path as one big gate and run Statistical Spice.... Danger! = Parallel Paths! & Topology! Considering single memory path as one big gate and run Statistical Spice.... Danger! = Parallel Paths! & Topology!.lib 4 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

13 DEVICE TO CORE LEVEL FULLY STATISTICAL CHARACTERIZATION FLOW Standard cell netlists Device variability Single Memory Path Netlist 5 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

14 DEVICE TO CORE LEVEL FULLY STATISTICAL CHARACTERIZATION FLOW Statistical SRAM Modeling [DAC10] Statistical SRAM Modeling [DAC10] In-House Stat. Characterizer [PATMOS09, DAC11] In-House Stat. Characterizer [PATMOS09, DAC11] Stat.Hspice, SiSmart/ELC/NCX,... Single Path Sensitivities (Stat. Hspice) Calculate Memory-wide Statistics Standard cell Liberty files Stat. Standard cell Libraries Memory cell Liberty files Statistical SRAM Libraries Standard cell netlists Device variability Single Memory Path Netlist 5 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

15 DEVICE TO CORE LEVEL FULLY STATISTICAL CHARACTERIZATION FLOW Statistical SRAM Modeling [DAC10] Statistical SRAM Modeling [DAC10] In-House Stat. Characterizer [PATMOS09, DAC11] In-House Stat. Characterizer [PATMOS09, DAC11] New for Statistical Flows Stat.Hspice, SiSmart/ELC/NCX,... Single Path Sensitivities (Stat. Hspice) Calculate Memory-wide Statistics Standard cell Liberty files Stat. Standard cell Libraries Memory cell Liberty files Statistical SRAM Libraries Standard cell netlists Device variability Single Memory Path Netlist 5 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

16 DEVICE TO CORE LEVEL FULLY STATISTICAL CHARACTERIZATION FLOW Statistical SRAM Modeling [DAC10] Statistical SRAM Modeling [DAC10] In-House “SSTA” tool [ISQED09] In-House “SSTA” tool [ISQED09] In-House Stat. Characterizer [PATMOS09, DAC11] In-House Stat. Characterizer [PATMOS09, DAC11] New for Statistical Flows DigiVAM (Design Compiler / ModelSim) Stat.Hspice, SiSmart/ELC/NCX,... Single Path Sensitivities (Stat. Hspice) Calculate Memory-wide Statistics Statistical Timing / Power Report Standard cell Liberty files Stat. Standard cell Libraries Memory cell Liberty files Statistical SRAM Libraries Standard cell netlists Device variability Single Memory Path Netlist ARM gate level netlist 5 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

17 SUPERPOSITION OF ALL CONDITIONS ALLOWS COMPARISON OF PVT: TIMING Critical Path Delay (memory& logic) 7 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 Intra-die: distribution shifts in all corners: memory effects dominate (worst case cell statistics) Inter-die: set final spread of distribution Total: combination of the two (shift and spread)

18 SUPERPOSITION OF ALL CONDITIONS ALLOWS COMPARISON OF PVT: TIMING Critical Path Delay (memory& logic) 7 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 Intra-die: distribution shifts in all corners: memory effects dominate (worst case cell statistics) Inter-die: set final spread of distribution Total: combination of the two (shift and spread)

19 SUPERPOSITION OF ALL CONDITIONS ALLOWS COMPARISON OF PVT: TIMING Critical Path Delay (memory& logic) 7 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 Intra-die: distribution shifts in all corners: memory effects dominate (worst case cell statistics) Inter-die: set final spread of distribution Total: combination of the two (shift and spread)

20 SUPERPOSITION OF ALL CONDITIONS ALLOWS COMPARISON OF PVT: TIMING Critical Path Delay (memory& logic) 7 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 Intra-die: distribution shifts in all corners: memory effects dominate (worst case cell statistics) Inter-die: set final spread of distribution Total: combination of the two (shift and spread)

21 BREAKING OUT THE INFLUENCE OF MEMORIES (INTRA-DIE) 8 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 Intra-die: Logic only (TT Corner for SRAM) No variations (TT Corner for Logic and SRAM)

22 BREAKING OUT THE INFLUENCE OF MEMORIES (INTRA-DIE) 8 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 Intra-die: Logic only (TT Corner for SRAM) Intra-die SRAM only (TT Corner for Logic) No variations (TT Corner for Logic and SRAM)

23 BREAKING OUT THE INFLUENCE OF MEMORIES (INTRA-DIE) Intra-die: Logic only (TT Corner for SRAM) Intra-die SRAM only (TT Corner for Logic) SRAM and Logic Intra-die (both considered) No variations (TT Corner for Logic and SRAM) 8 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

24 BREAKING OUT THE INFLUENCE OF MEMORIES: INTRA-DIE VARIATION 75% 100% 0% 33 33 8 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 50% Intra-die: Logic only (TT Corner for SRAM) Intra-die SRAM only (TT Corner for Logic) Intra-die: SRAM & Logic No variations (TT Corner for Logic and SRAM)

25 BREAKING OUT THE INFLUENCE OF MEMORIES: INTRA-DIE VARIATION 75% 100% 0% 33 33 8 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 50% Intra-die: Logic only (TT Corner for SRAM) Intra-die SRAM only (TT Corner for Logic) Intra-die: SRAM & Logic No variations (TT Corner for Logic and SRAM) SRAM

26 INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926 Intra-die: SRAM & Logic 33 33 9 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 No variations (TT Corner for Logic and SRAM)

27 INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926 Intra-die: SRAM & Logic 33 33 Inter-die :SRAM and Logic 9 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 No variations (TT Corner for Logic and SRAM)

28 INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926 Intra-die: SRAM & Logic Total convolution intra- & inter-die (full core) 33 33 Inter-die :SRAM and Logic 9 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 No variations (TT Corner for Logic and SRAM)

29 INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926 Intra-die: SRAM & Logic Total convolution intra- & inter-die (full core) 33 33 Inter-die :SRAM and Logic 9 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 No variations (TT Corner for Logic and SRAM) 60% 100% 0% 40%

30 INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926 Intra-die: SRAM and Logic Total convolution intra- & inter-die (full core) 33 33 Inter-die :SRAM and Logic 9 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 No variations (TT Corner for Logic and SRAM) 60% 100% 0% 40% Intra- die

31 INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926 Intra-die: SRAM and Logic Total convolution intra- & inter-die (full core) 33 33 Inter-die :SRAM and Logic 9 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 No variations (TT Corner for Logic and SRAM) 60% 100% 0% 40% Intra- die SRAM

32 CONCLUSIONS Variability impact of 32nm HK-MG technology on a ARM926 quantified: Intra-die:Total: 75% 30% Risk of under/over- design if margin concluded from SRAM typical/worst case corner only State-of-art (in-house) statistical memory characterization used for SRAM.lib generation SRAM 10 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

33 CONCLUSIONS Variability impact of 32nm HK-MG technology on a ARM926 quantified: Intra-die:Total: 75% 30% Risk of under/over- design if margin concluded from SRAM typical/worst case corner only State-of-art (in-house) statistical memory characterization used for SRAM.lib generation SRAM Intra- die 10 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

34 CONCLUSIONS Variability impact of 32nm HK-MG technology on a ARM926 quantified: Intra-die:Total: 75% 30% Risk of under/over- design if margin concluded from SRAM typical/worst case corner only State-of-art (in-house) statistical memory characterization used for SRAM.lib generation SRAM Intra- die SRAM 10 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

35 CONCLUSIONS Variability impact of 32nm HK-MG technology on a ARM926 quantified: Intra-die:Total: 75% 30% Risk of under/over- design if margin concluded from SRAM typical/worst case corner only State-of-art (in-house) statistical memory characterization used for SRAM.lib generation SRAM 10 Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011 Intra- die SRAM

36 THANK YOU! Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

37 SYNTHESIS CONDITIONS FOR ARM926 Test Vehicle: ▸ ARM926EJS -6 different SRAM types -23 instances -300 devices in access path ▸ Target: 500MHz Logic library: ▸ 80 cells reduced library ▸ 32nm node ▸ RVT flavour Memory ▸ Pre-production SRAM ▸ 32nm node ▸ Programmable size Synthesis Conditions Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011

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