Download presentation

Presentation is loading. Please wait.

Published byMarquis Hilman Modified over 2 years ago

2
On the Need for Statistical Timing Analysis Farid N. Najm University of Toronto f.najm@utoronto.ca

3
3 Introduction n Increased process variability leads to chip timing variability and lower timing yield n Traditionally, corner-analysis (worst-case files) has been used to manage timing variability l Corner analysis has some disadvantages n Statistical Static Timing Analysis (SSTA) has been proposed as an alternative approach l SSTA has its own disadvantages n Perhaps an alternative “best of both worlds” approach is required: l Use statistical analysis to better choose the corners or the margins to be used in a traditional STA approach

4
4 Generation of Corner-Case Files n Principal Components Analysis de-correlates SPICE parameters and captures bulk of variations n Process parameter corners chosen to maximize MOSFET performance yield

5
5 Disadvantages of Corner Analysis n Some disadvantages: l Corners should maximize circuit yield, not device yield u Goal is to bracket most (say, 99.73%) of what? 1. individual process variable space? 2. typical transistor strength? 3. typical gate/cell delay? 4. overall circuit performance? è Ideally, one would like #4, but traditionally go with #2 l There are too many corners l Cannot take care of within-die variations l Corner analysis is overkill u One is capturing much more yield (performance spread) than one really needs to l Cannot determine how robust the design is

6
6 Too Many Corners n With more process parameters, the number of process corners increases exponentially n However, there have been recent proposals to reduce the number of corners to be considered l Corner clustering (Sengupta et al., ISQED-04) l This method also allows one to choose corners so as to bracket circuit performance, instead of device performance Quadratic circuit response, RSM: g(X) = a + bX + X T BX Solution: X vector that minimizes and maximizes g(X) u Cluster corners that are close in the parameter space

7
7 Case Files & Intra-Die Variations n Traditional corner analysis cannot take care of within- die variations l Heuristic techniques are used within some traditional STA tools to approximately take care of within-die effects n The crux of the problem lies in the systematic within-die variations l Random within-die variations “cancel out” on a path u They don’t exactly cancel out, but their net result is reduced n The overall impact of within-die variations on circuit delay arguably remains small compared to die-to-die variations (S. Samaan, ICCAD-04)

8
8 Too Much Guardbanding n Corner analysis becomes “overkill” when the implicit yield target becomes too large l Not always the case in corner analysis! Assume that a nominal value of yield is what covers the ± 3 of a standard normal distribution: Y 0 = 99.73% n Whether corner analysis is overkill or not depends on the performance metric If g(X) = Xi (i = 1,…, n), then Y (3n 1/2 ) - (-3n 1/2 ) > Y 0 Setting Xi at ± 3 is overkill If g(X) = max (Xi) then Y n (3) - n (-3) < Y 0 Setting Xi at ± 3 is NOT overkill n It also depends on the shape of the acceptability region

9
9 Assessment n The straightforward nature of corner-case analysis has made it the method of choice in industry n It has some limitations: l Need to determine corners based on circuit performance l Location of corners depends on acceptability region l Need to reduce the number of corners to be covered l Cannot determine how robust the design is n Nevertheless, criticisms do not dismiss this approach altogether

10
10 Statistical Timing Analysis n Recently, “Statistical Static Timing Analysis” (SSTA) has been proposed l Deal with circuit timing uncertainty l An alternative to corner analysis n Basic Idea: l Propagate delay distributions, instead of deterministic delays, in the timing graph u Compute node and path delay distributions l Estimate the distribution of circuit delay as the joint distribution of path delays l Find the chip timing yield from circuit delay distribution

11
11 Statistical Timing Analysis n How to handle different types of delay correlations ? l Within-die systematic correlation l Path sharing (reconvergent fanout) l Dependence on global sources of variations n How to propagate distributions in the timing graph ? l The statistical MAX function l Statistical SUM function n What types of distributions to use ? l Gaussian, or arbitrary distributions ? n Distinct trends: l Block-based statistical timing l Path-based statistical timing

12
12 Block-Based SSTA n Propagate distributions of arrival times in the timing graph of the block to get circuit delay distribution n Path distributions are available only indirectly

13
13 The MAX Operation n Arrival times are “MAX-ed” at the nodes of the graph l Circuit delay distribution is obtained on the primary outputs n The various methods differ in: l How the MAX operation is performed l Assumptions on the nature of the distributions (Gaussian/not) l Whether and how correlation is taken care of

14
14 Overview: Block-Based Methods n A key difference among block-based methods lies in whether delays are assumed Gaussian or arbitrary n Two Gaussian approaches both use decomposition, but differ in what underlying variables are used l Visweswariah et al. derive correlations from global sources of variation l Sapatnekar et al. perform PCA on the spatial correlations n Two non-Gaussian approaches differ in the propagation algorithm of arrival times l Blaauw et al. use conservative bounds on delay distributions l Devgan et al. use piece-wise linear approximations

15
15 Path-Based Methods n Path delay distributions are expressed as functions of the underlying sources of variation l Gate delay distributions are added to get path delay distribution l Literature by: Nassif, Jess, Orshansky, Bowman n Circuit delay distribution is obtained from the joint probability of path delays l Circuit delay = MAX(all path delays) n Flow: l Enumerate all critical paths l Estimate path delay distributions l Use multi-dimensional integration to combine all paths l Estimate the timing yield

16
16 Assessment n The problem of propagating delay distributions along paths or through blocks is now “solved” n Yet, this does not mean that SSTA is now “solved”! n Key problems in the proposed methods of SSTA l What does one do with all these distributions?! l Unless if the full chip is “timed” flat, require change in methodology: cannot “time” a path or block in isolation l Correlation handling requires layout information, hence cannot be used pre-placement during circuit design/optimization l Not clear how to get correlation statistics from the process; a disconnect between process and EDA

17
17 Practical SSTA n Desirable features of a practical SSTA approach: l Must require minimal statistical process data l Must account for correlated and uncorrelated variations l Must be usable pre-placement to enable design optimization l Must be applicable to “early design” with uncertain circuitry, in order to allow one to time a path/block in isolation n One can envision three types of SSTA: l Process-specific, not design-specific, during early design l Design-specific, not placement-specific, during circuit design l Placement-specific, during physical design n A mix of the three types of SSTA would constitute a practical framework for managing timing variability

18
18 An Early Design Approach n A recent approach (Najm and Menezes, DAC-04) is applicable during early design l Employ notion of generic paths to develop an approach which is process-specific, not design-specific n The ability to handle early (uncertain) design is key to being able to time a path/block in isolation! n Shift focus from the specific design to a design type l What are a typical transistor/gate in this technology? l What is a typical path length in this class of design? l Assume the circuit or block consists of a large number of such “generic paths”

19
19 Overview

20
20 Conclusions n Process variability is a key factor of timing yield loss and deterioration of circuit performance n Traditional corner analysis has some limitations, but they are not insurmountable n Statistical timing analysis is being proposed as an alternative, but it has its own limitations n Perhaps one can have it both ways l Combine features of statistical analysis and corner-case files l Derive virtual corners and timing margins for a yield-aware timing verification n This continues to be an active research topic

Similar presentations

OK

Penn ESE535 Spring 2013 -- DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015 Statistical Static Timing Analysis.

Penn ESE535 Spring 2013 -- DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015 Statistical Static Timing Analysis.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on blood stain pattern analysis jobs Ppt on chapter 12 electricity company Ppt on review writing worksheets Ppt on plane table surveying Ppt on electricity generation from municipal solid waste Ppt on contact and noncontact force Ppt on history of olympics for kids Ppt on differential aptitude test Ppt on nepali culture and tradition Keynote opening ppt on iphone