1. Anjali Supekar *, Mohita Batra *, Rakesh Gulati *, Shahabuddin Qureshi °, Hina Mushir #, Prashant Pandey #, Samant Paul °, Seema Jaiswal ° * Automation Team ° IP Team # Silicon Test and Debug Team ST MICROELECTRONICS

2. Due to reduced margins in the SOC design, number of critical path are increasing. Digital timing analysis methods are shaking hands with spice validation methodologies resulting in mixed signal analysis modes. CURRENT METHODS:  Highly time consuming  Use complete spice (large size) OUR INTEND:  Simulating any path of any hierarchy of a design  Quick & flexible analysis of true behavior of the path over wide range of operating conditions  Use output of the tool to optimize the design. However…..However….. MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS

3. Mixed Mode Multiple corner but Time Taking Huge pattern set STA Limited corner REQUIRED TOOL Multiple Corner Fast Specific Coverage (Flat Design) Out of SIGN OFF Improved Accuracy Unable to characterize small portion of hard IP MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS With change in technologies, there was a need to reduce the “extra margin” under consideration in order to get characterization for a small area leading to more optimistic approach. With the existing options (Sign Off /Mixed Mode), analysis was possible only at full block level and hierarchical analysis was not supported. For such huge hierarchies we have developed a solution which lies between HDL and mixed mode analysis. The solution provides extraction at multiple corners and increased accuracy Less Accurate Large coverage (Not specific, unsuitable for flat design)

4. MOTIVATIONTOOL FLOWRESULTSENHANCEMENTSMemoryMemory Pulse Generator SensorSensor Q1 LSB Load Clock Q2 MSB Source Clock Pulse Clock Pulse Propagation Clock Slope Q Slope Expected Access Time on Silicon: T A Actual Access Time obtained from CAD: T AA CAD Correction Factor (CCF) Δ = T A - T AA T A = Δ + T AA T A = Δ + T AA CK & Q PULSE FROM MEM CCF Total Contribution (4-1) 11 APPLICATION UNDER STUDY: CAD CORRECTION FACTOR Balancing Contribution (2-1)Path Contribution ( 4-3) PulseGen Contribution (3-2) 2233 44

5. Memory Q CK PULSEGEN (Sensor lib) CUT1 Test chip logic for pulse propagation And mixing to a central location Sensor Digital Output Central Location (Pulse To digital Conversion) Memory Q CK PULSEGEN (Sensor lib) CUTn Error sources in T AA T AA measurement T ERROR-TC : Rise (Edge) Delay – Fall (Edge) Delay Pulse variation Error depends on input Slopes. Error of the order of medium size inverter delay This value (extracted from STA) is provided in testdoc on signoff conditions for each cut -Balanced structure (Controlled placement and routing etc) MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS PROBLEM STATEMENT: T AA  The T AA measured on chip measurement (Sensor) is going below CAD fast limits. T AA  CAD analysis on T AA pulse propagation from memory to Sensor shows reduction in pulse width

6. MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS Spice Modification for all CUTs Write simulation stubs for Clock slope Simulation Setup files PVT Excel Spice Invoke EDA Simulator for Clock slope simulation Compile Clock slopes for all CUTs in Tool Internal Format Generate/Copy Load-slope XLS and write CCF Simulation stubs Invoke EDA Simulator for CCF simulation Compile CCF for all CUTs in a predefined format Clock Slopes XLS Simulation Environment Spice Simulator Load Slopes XLS Detailed CCF CCF TOOL FLOW

7. The PVT Generator is an automation tool written in VB which facilitates the generation of PVT sheet from the standard input sources from the Front End and Sensor dataPVT PVT Mapping Test Spec Sheet Clock Slope INPUTS Memory Test Specification Clock Slope Delivered along with SPICE files PVT Mapping Information Simulation and Spice Extraction Temperature Process and RC Extraction MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS

8. Invoke the Macro from the Excel Tool Furnish the memory test spec excel and select the appropriate sheet Furnish the Clock Slope csv and select the appropriate sheet Map the simulation temperature to the available spice extraction temperature Map the process to corresponding RCExtraction and provide CUT predecessor MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS PVT GENERATOR FLOW

9. Spice Correction Slope Calculation CCFCalculation MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS CCF Flow involves parsing of PVT Topsheet which contains CUT details and PVT information for CCF calculations. For Spice simulation, it processes Spice to be directly used, write simulation stubs for each cut, to calculate Clock slopes and CCF. Simulation Environment : Automation supports, Writing simulation files and invoking Simulation Environment for launching of clock slope simulations and CCF simulations. Flow supports Compilation of the Clock slopes and CCF for all the CUTs in tool internal format

10. Manual (Before Automation) Thorough knowledge about Spice files, its extraction, modification, Eldo simulation and other tools for calculating CCF Set-up Time was approximately 1-2 days (includes spice extraction, correction, run files, stimuli and other data files) Simulation was initially sequential. Even if it was parallel, there was no tracking mechanism. Simulation time was approximately 4-5 days Result compilation was tedious as there were many excel sheets having huge data which was unmanageable. It took approximately 8- 10 hours No debug options After Automation User need not be aware of any simulation tools. Tool is user friendly and no prior knowledge required. Set-up Time reduced to half an hour Parallel simulation along with tracking mechanism. At any point user can check simulation status of any CUT. Simulation time reduced to 4-5 hours Result compilation made easy with proper monitoring of all sheets for each cut. Time reduced to 5-6 minutes Easy Debug options MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS 90% of user time is saved

11. 11 MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS PURE MEMORY CAD NEW MEMORY CAD V1V2V3V4V5 V5 > V1 T5<T1 T1 T2 T3 T4 T5 CAD v/s Silicon Analysis of a Testchip CAD v/s SI Aligned with Increased Accuracy of new CCF CAD v/s SI Aligned with Increased Accuracy of new CCF CAD CORRECTION FACTOR SYSTEM ACCURACY

12. Testchip Process Sensor Memory Ring Oscillators MOTIVATIONTOOL FLOWRESULTSENANCEMENTS Process Sensor Block (for Sensor Data Analysis) Temperature sensitivity voltage sensitivity RC Impact Impact of device sensitivity Process Sensor Block (for Sensor Data Analysis) Temperature sensitivity voltage sensitivity RC Impact Impact of device sensitivity Standard Cell RO Block CAD Data Generation for any type of architecture (flops, mux, etc) easy analysis (currents, timing, frequency) CAD Correction Factor (CCF) + MCF (Memory) A TAA error value calculation for test chips is an important step to calculate path contribution to extract the deviation of CAD from Silicon. CAD Correction Factor (CCF) + MCF (Memory) A TAA error value calculation for test chips is an important step to calculate path contribution to extract the deviation of CAD from Silicon. Potential Applications Proposed solution addresses different components of SOC. ENHANCEMENTSMOTIVATION

13. TOOL FLOWRESULTSENHANCEMENTS AUTOMATIC CAD CORRECTION FACTOR GENERATION THROUGH MCF EXISTING FLOW NEW OPTIMIZED FLOW 13 Clock Slope and Q load @ multiple corners Extract slope @ multiple corners Extract Load slopes @ multiple corners Extracts CCF @ multiple corners Extract memory CAD manual adjustment for CCF Memory team do delivery of CAD Data to Test team Clock Slope / load @ multiple corners simulations for Unified CAD Data {CCF included} CAD Data Delivery Cycle time + No. of simulations " Faster & Accurate" CAD data generation for Improving Accuracy for CAD vs Si analysis. 3X Gain TESTCHIP TEAM MEMORY TEAM TESTCHIP TEAM MEMORY TEAM

14. T ool fully automates the Sensor Design Analysis and CAD Data Generation for Silicon validation. MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS Temperature SensitivityVoltage SensitivityRC ImpactImpact of device sensitivity Sensor Data Analysis Temperature Sensitivity RC Impact Process Sensor Block Voltage Sensitivity

15. Enable this tool for SoC designers at physical implementation stage. Option for generating GDS and CDL of a specific portion of targeted block of SOC taking DEF as input and then extracting Spice from GDS and CDL. Analyzing Critical paths using Actual Spice Simulations MOTIVATIONTOOL FLOWRESULTSENHANCEMENTS