1. ES 244: Digital Logic Design Chapter 2 Chapter 2: Combinational Systems Adapted from Alan Marcovitz’s Introduction to Logic and Computer Design Uchechukwu Ofoegbu Temple University

2. ES 244: Digital Logic Design Chapter 2Riddle Four switches can be turned on or off. One is the switch for the incandescent overhead light in the next room, which is initially off, but you don't know which. The other three switches do nothing. From the room with the switches in it, you can't see whether the light in the next room is turned on or off. You may flip the switches as often and as many times as you like, but once you enter the next room to check on the light, you must be able to say which switch controls the light without flipping the switches any further. (And you can't open the door without entering, either!) How can you determine which switch controls the light?

3. ES 244: Digital Logic Design Chapter 2 Begins with a verbal description of the intended system, known as the PROBLEM STATEMENT A block diagram of the system should be developed The desired objectives and constraints Design Process for Combinational Systems

4. ES 244: Digital Logic Design Chapter 2 1. 1.A system with four inputs, A, B, C, and D, and one output, Z, such that Z = 1 iff three of the inputs are 1. 2. 2.A single light (that can be on or off) that can be controlled by any one of three switches. One switch is the master on/off switch. If it is off, the lights are off. When the master switch is on, a change in the position of one of the other switches (from up to down or from down to up) will cause the light to change state. 3. 3.A system to do 1 bit of binary addition. It has three inputs (the 2 bits to be added plus the carry from the next lower order bit) and produces two outputs, a sum bit and a carry to the next higher order position. Illustrations

5. ES 244: Digital Logic Design Chapter 2 4. 4.A system that has as its input the code for a decimal digit, and produces as its output the signals to drive a seven- segment display, such as those on most digital watches and numeric displays. 5. 5.A system with nine inputs, representing two 4-bit binary numbers and a carry input, and one 5-bit output, representing the sum. (Each input number can range from 0 to 15; the output can range from 0 to 31.) Illustrations

6. ES 244: Digital Logic Design Chapter 2 1. 1.Represent each of the inputs and output in binary. This is sometimes taken care of in the problem statement (ex 1, 3, 5) 2. 2.Formalize the design specification either in the form of a truth table or of an algebraic expression. There are 2 n input combinations for n inputs in a truth table. Truth tables are written in binary order to avoid omissions. If necessary, break the problem into smaller sub- problems before or after creating the truth tables. Design Steps

7. ES 244: Digital Logic Design Chapter 2 3. 3.Simplify the description. Most times expressions have to be converted to algebraic forms Several techniques exist for reducing complexity of algebraic forms 4. 4.Implement the system with the available components, subject to the design objectives and constraints. Gates are the most common components A gate is a network with one output The less number of gates required, the more desirable the system is, since each signal passing through a gate introduces a delay in the system. More complex systems can be used in addition to gates (ex. Adders, decoders, e.t.c.). Design Steps

8. ES 244: Digital Logic Design Chapter 2 Don’t cares occur when The output is not specified for all input combinations, so for the remaining input combinations, it doesn’t matter There are input combinations that don’t occur in the system Flip-flops – one systems drives another When we just don’t care Don’t cares are represented by X in a truth table. The output of the combination could either be a 1 or a 0. Don’t Care Conditions

9. ES 244: Digital Logic Design Chapter 2 Developing Truth Tables 1. 1.A system with four inputs, A, B, C, and D, and one output, Z, such that Z = 1 iff three of the inputs are 1.

10. ES 244: Digital Logic Design Chapter 2 2. 2.A single light (that can be on or off) that can be controlled by any one of three switches. One switch is the master on/off switch. If it is off, the lights are off. When the master switch is on, a change in the position of one of the other switches (from up to down or from down to up) will cause the light to change state.

11. ES 244: Digital Logic Design Chapter 2 4. A system that has as its input the code for a decimal digit, and produces as its output the signals to drive a seven-segment display

12. ES 244: Digital Logic Design Chapter 2

13. Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, b in, and inputs x, y, that produces an a difference output, d, and a borrow output, b out. b in xyb out d 00000 001?? 010 011 100 101 110 111 a.0 0 b.0 1 c.1 0 d.1 1

14. ES 244: Digital Logic Design Chapter 2 Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, b in, and inputs x, y, that produces an a difference output, d, and a borrow output, b out. b in xyb out d 00000 00111 010?? 011 100 101 110 111 a.0 0 b.0 1 c.1 0 d.1 1

15. ES 244: Digital Logic Design Chapter 2 Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, b in, and inputs x, y, that produces an a difference output, d, and a borrow output, b out. b in xyb out d 00000 00111 01001 011?? 100 101 110 111 a.0 0 b.0 1 c.1 0 d.1 1

16. ES 244: Digital Logic Design Chapter 2 Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, b in, and inputs x, y, that produces an a difference output, d, and a borrow output, b out. b in xyb out d 00000 00111 01001 01100 100?? 101 110 111 a.0 0 b.0 1 c.1 0 d.1 1

17. ES 244: Digital Logic Design Chapter 2 Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, b in, and inputs x, y, that produces an a difference output, d, and a borrow output, b out. b in xyb out d 00000 00111 01001 01100 10011 101?? 110 111 a.0 0 b.0 1 c.1 0 d.1 1

18. ES 244: Digital Logic Design Chapter 2 Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, b in, and inputs x, y, that produces an a difference output, d, and a borrow output, b out. b in xyb out d 00000 00111 01001 01100 10011 10110 110?? 111 a.0 0 b.0 1 c.1 0 d.1 1

19. ES 244: Digital Logic Design Chapter 2 Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, b in, and inputs x, y, that produces an a difference output, d, and a borrow output, b out. b in xyb out d 00000 00111 01001 01100 10011 10110 11000 111?? a.0 0 b.0 1 c.1 0 d.1 1

20. ES 244: Digital Logic Design Chapter 2 Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, b in, and inputs x, y, that produces an a difference output, d, and a borrow output, b out. b in xyb out d 00000 00111 01001 01100 10011 10110 11000 11111

21. ES 244: Digital Logic Design Chapter 2 3. 3.Simplify the description. Most times expressions have to be converted to algebraic forms Several techniques exist for reducing complexity of algebraic forms 4. 4.Implement the system with the available components, subject to the design objectives and constraints. Gates are the most common components A gate is a network with one output The less number of gates required, the more desirable the system is, since each signal passing through a gate introduces a delay in the system. More complex systems can be used in addition to gates (ex. Adders, decoders, e.t.c.). Switching Algebra

22. ES 244: Digital Logic Design Chapter 2

23. Literal: The appearance of a variable or its complement. Product Term: one or more literals connected by AND operators. Standard product term: Also called minterm product term that includes each variable of the problem, either uncomplemented or complemented. Sum of products expression (often abbreviated SOP) one or more product terms connected by OR operators. A canonical sum or sum of standard product terms: a sum of products expression where all of the terms are standard product terms. Definitions

24. ES 244: Digital Logic Design Chapter 2 A Minimum Sum of Products expression: one of those SOP expressions for a function that has the fewest number of product terms. If there is more than one expression with the fewest number of terms, then minimum is defined as one or more of those expressions with the fewest number of literals. (1)xyz + xyz + xyz + xyz + xyz5 terms, 15 literals (2)xy + xy + xyz3 terms, 7 literals (3) xy + xy + xz3 terms, 6 literals (4) xy + xy + yz3 terms, 6 literals Definitions

25. ES 244: Digital Logic Design Chapter 2 xyz + xyz + xyz + xyz + xyz5 terms, 15 literals = (x’yz’+x’yz)+(xyz + xyz) + xyzassociative p2 = x’y(z+z’) + xy’(z+z’) + xyzdistributive p8 = x’y.1 +xy’.1 +xyzcomplement p5 = x’y + xy’ + xyzidentity p3 Simplification Down to three terms and seven literals

26. ES 244: Digital Logic Design Chapter 2 xyz + xyz + xyz + xyz + xyz + xy’z5 terms, 15 literals = (x’yz’+x’yz)+(xyz + xyz) + (xyz + xy’z) associative p2 = x’y + xy + xzadjacency p9 Simplification Down to three terms and six literals Reduce the number of literals by adding a second copy of xy’z (or x’yz), based on P6a – indempotency.

27. ES 244: Digital Logic Design Chapter 2Simplification

28. Simplification

29. Sum Term: one or more literals connected by OR operators. Standard sum term: also called a maxterm a sum term that includes each variable of the problem, either uncomplemented or complemented. Product of sums expression (POS): one or more sum terms connected by AND operators. Canonical product or product of standard sum terms: a product of sums expression where all of the terms are standard sum terms. SOP:xy + xy + xyz POS:(x + y)(x + y)(x + z) both: x + y + z or xyz neither:x(w + yz) or z + wxy + v(xz + w) Definitions

30. ES 244: Digital Logic Design Chapter 2 g = (w’ + x’ + y) (w + x’+ y + z’) = x’ + y + w’(w + z’)distributive (P8b) = x’ + y + w’z’simplification (p10b) = (x’ + y + w’) (x’ + y + z’)distributive (P8b) Simplification of Functions in Maxterm Form

31. ES 244: Digital Logic Design Chapter 2 Minimum sum of product implementation of f. Circuit with only uncomplemented inputs. Implementation of Logic Gates f = x’y + xy’ + xz

32. ES 244: Digital Logic Design Chapter 2 Implementation of Logic Gates

33. ES 244: Digital Logic Design Chapter 2 Implementation of Logic Gates a.d = n’+c(h+s) (n+c’(h+s)) b.d = (n’c) + (hs) + n(hs) + c c.d = n’c(h+s) + n(c’+(hs)) d.D = n’c(ns) + n(hs)c =

34. ES 244: Digital Logic Design Chapter 2 Proof of DeMorgan’s theorem. De Morgan’s Theorem P11a. (a+b)’ = a’b’ P11b. (ab)’ = a’+b’ Please note: (a’+b’) != a’+b’ (ab)’ != a’b’ De Morgan’s Theorem is generally used to find the complement of an expression find the complement of an expression

35. ES 244: Digital Logic Design Chapter 2 De Morgan’s Theorem - Example Find the complement of f = wx’y +xy’ +wxz Note that f is in SOP so f’ will be in POS We could apply DeMorgan’s Theorem repeatdely – –f’ = (wx’y +xy’ +wxz)’ – –f’ = (wx’y)’(xy’)’(wxz)’ – –f’ = (w’x+y’)(x’+y)(w’+x’+z’) Or we could follow these set of rules – –Complement each variable – –Replace every AND by Or and every OR by AND – but make sure you keep the order of operation

36. ES 244: Digital Logic Design Chapter 2 De Morgan’s Theorem - Example Find the complement of f = ab +b’c + c’d a. a.f’ = (a’ + b’+ b + c’ + c + d’) b. b.f’ = (a’ + b’+ b + c’ + c + d’)’ c. c.f’ = a’b’+bc’+cd’ d. d.f’ = (a’ + b’)( b + c’) (c + d’) e. e.f’ = (a’ + b’)’( b + c’)’(c + d’)’

37. ES 244: Digital Logic Design Chapter 2 1 2e,f 3f 5 8 12a 13c 14 18 In groups

38. ES 244: Digital Logic Design Chapter 2 f = ab + ab + ab From the truth table to Algebraic Expressions

39. ES 244: Digital Logic Design Chapter 2 From the truth table to Algebraic Expressions

40. ES 244: Digital Logic Design Chapter 2Example ABCff’ 00001 00110 01010 01110 10001 10101 11010 11110 f(A,B,C) = Σm(1,2,3,6,7) = ? f’(A,B,C) = ? a.A’B’C’ + AB’C’ + AB’C b.B + C + D + G + H c.A’B’C + A’BC’ + A’BC + ABC’+ABC d.ABC’ + AB’C + AB’C’+ A’B’C + A’b e.ABC + A’BC+A’BC’ a.Σm(1,2,3,6,7)’ b.Σm(0,4,5) c.Σm(A’B’C’ + AB’C’ + AB’C)

41. ES 244: Digital Logic Design Chapter 2 Don’t Cares Inputf 0000 001X 0101 0111 1000 101X 1101 1111 f(A,B,C) = Σm(2,3,6,7)+ Σd(1,5)

42. ES 244: Digital Logic Design Chapter 2 20 22 23 27 In groups