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1-Given the Boolean function F = xy’z + x’y’z + w’xy + wx’y + wxy (a) Obtain the truth table of the function. (b) Draw the logic diagram using the original.

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Presentation on theme: "1-Given the Boolean function F = xy’z + x’y’z + w’xy + wx’y + wxy (a) Obtain the truth table of the function. (b) Draw the logic diagram using the original."— Presentation transcript:

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2 1-Given the Boolean function F = xy’z + x’y’z + w’xy + wx’y + wxy (a) Obtain the truth table of the function. (b) Draw the logic diagram using the original Boolean expression. (c) Simplify the function to a minimum number of literals using Boolean algebra. (d) Obtain the truth table of the function from the simplified expression and show that it is the same as the one in part (a) (e) Draw the logic diagram from the simplified expression and compare the total number of gates with the diagram of part (b).

3 2- Design a 4-bit full subtractor using Full adder block diagram 3 A hint X – Y = X + ( Y + 1) = X + ( 2’s Complement of Y) A hint X – Y = X + ( Y + 1) = X + ( 2’s Complement of Y)

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5 3- With the aid of K-map, draw the circuit of the priority encoder 4-to-2 (hint: X is don’t care condition ) 4- Combine two of 2-to-4 decoders to design a 3-to-8 decoder 5- Complete the above K-maps of the 7 segments display 5

6 6 1- With the aid of K-map, draw the circuit of the priority encoder 4-to 2 (hint: X is don’t care condition )

7 7 2- Combine two of 2-to-4 decoders to design a 3-to-8 decoder (Expansion) The block diagram zYxzYx

8 8 X Y Z

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10 6-Design the digital logic circuit of 8-to-1 MUX using two 4-to-1 and a 2-to-1 MUX 7-Design a 16-to-1 multiplexer using four of 4-to-1 multiplexers and one 4-to-1 8-Design 1-to-8 De-Multiplexer 10

11 1- Design the digital logic circuit of 8-to-1 MUX using two 4-to- 1 and a 2-to-1 MUX 11

12 8-to-1 MUX Truth table 2-to-1 MUX Truth table 12

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14 2- Design a 16-to-1 multiplexer using with four of 4-to-1 multiplexers 14

15 15 S3 S2 S1 S0 Q 0 0 I0I0 0 0 0 1 I1I1 0 0 1 0 I2I2 0 0 1 1 I3I3 0 1 0 0 I4I4 0 1 I5I5 0 1 1 0 I6I6 0 1 1 1 I7I7 1 0 0 0 I8I8 1 0 0 1 I9I9 1 0 I 10 1 0 1 1 I 11 1 1 0 0 I 12 1 1 0 1 I 13 1 1 1 0 I 14 1 1 I 15 The truth table of 16-to-1 Multiplexer

16 3- Design 1-to-8 De-Multiplexer 16 S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 0 0 0 on 0 0 0 0 0 0 0 0 0 1 0 on 0 0 0 0 0 0 0 1 0 0 0 on 0 0 0 0 0 0 1 1 0 0 0 on 0 0 0 0 1 0 0 0 0 0 0 on 0 0 0 1 0 1 0 0 0 0 0 on 0 0 1 1 0 0 0 0 0 0 0 on 0 1 1 1 0 0 0 0 0 0 0 on

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18 H.W The submission has to be by the end of this week H.W The submission has to be by the end of this week Write your full name and the group number on the answer sheet 1- Draw the state diagram of T Flip Flop 2- From the below block diagram of a counter : a) What kind of triggering is used? b)With the aid of timing diagram clarify the sequence of the main states Qs that is possible by this counter assuming their initial states are 0 c)What is the new result if we replace the JK flip flop with the T flip flop in this counter and why? 18

19 H.W H.W 3- From the following logic circuit draw the timing diagram for ‘Q’. Assume ‘Q’ has an initial value of ‘0’ 19

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