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Assignments The submission has to be by the end of this week Write your full name and the group number on the answer sheet

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1-Given the Boolean function F = xy’z + x’y’z + w’xy + wx’y + wxy (a) Obtain the truth table of the function. (b) Draw the logic diagram using the original Boolean expression. (c) Simplify the function to a minimum number of literals using Boolean algebra. (d) Obtain the truth table of the function from the simplified expression and show that it is the same as the one in part (a) (e) Draw the logic diagram from the simplified expression and compare the total number of gates with the diagram of part (b).

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**2- Design a 4-bit full subtractor using Full adder block diagram**

A hint X – Y = X + ( Y + 1) = X + ( 2’s Complement of Y)

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3- With the aid of K-map, draw the circuit of the priority encoder 4-to-2 (hint: X is don’t care condition ) 4- Combine two of 2-to-4 decoders to design a 3-to-8 decoder 5- Complete the above K-maps of the 7 segments display

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1- With the aid of K-map, draw the circuit of the priority encoder 4-to 2 (hint: X is don’t care condition )

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H.W 2- Combine two of 2-to-4 decoders to design a 3-to-8 decoder (Expansion) The block diagram z Y x

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X Y Z

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6-Design the digital logic circuit of 8-to-1 MUX using two 4-to-1 and a 2-to-1 MUX 7-Design a 16-to-1 multiplexer using four of 4-to-1 multiplexers and one 4-to-1 8-Design 1-to-8 De-Multiplexer

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H.W 1- Design the digital logic circuit of 8-to-1 MUX using two 4-to-1 and a 2-to-1 MUX

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**8-to-1 MUX Truth table 2-to-1 MUX Truth table c**

c b a Q I0 I1 I2 I3 I4 I5 I6 I7 c Q Q1 1 Q2

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**2- Design a 16-to-1 multiplexer using with four of 4-to-1 multiplexers**

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**The truth table of 16-to-1 Multiplexer**

S S S1 S0 Q I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

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**3- Design 1-to-8 De-Multiplexer**

S S S0 Q Q Q2 Q3 Q Q Q Q7 on on on on on on on on

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H.W The submission has to be by the end of this week Write your full name and the group number on the answer sheet 1- Draw the state diagram of T Flip Flop 2- From the below block diagram of a counter : What kind of triggering is used? With the aid of timing diagram clarify the sequence of the main states Qs that is possible by this counter assuming their initial states are 0 What is the new result if we replace the JK flip flop with the T flip flop in this counter and why?

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H.W 3- From the following logic circuit draw the timing diagram for ‘Q’. Assume ‘Q’ has an initial value of ‘0’

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Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved.

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