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Increasing Design Changeability using Dynamical Partial Reconfiguration KIP Heidelberg Norbert Abel, Udo Kebschull.

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Presentation on theme: "Increasing Design Changeability using Dynamical Partial Reconfiguration KIP Heidelberg Norbert Abel, Udo Kebschull."— Presentation transcript:

1 Increasing Design Changeability using Dynamical Partial Reconfiguration KIP Heidelberg Norbert Abel, Udo Kebschull

2 General DAQ Setup Page 2 Norbert Abel & Udo Kebschull, KIP Heidelberg DAQ (Cluster) Beam Collision Detectors DAQ (FPGAs) FEE (ADC)

3 DAQ Setup Page 3 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 (Communication & Filtering) Board C1 (Communication & Combining) FPGA

4 Reconfiguration Page 4 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 (Communication & Filtering) Board C1 (Communication & Combining) FPGA Functionality: Filter 2.4

5 Reconfiguration Page 5 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 (Communication & Filtering) Board C1 (Communication & Combining) FPGA Reconfiguration Process X X X X X

6 Reconfiguration Page 6 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 (Communication & Filtering) Board C1 (Communication & Combining) FPGA Functionality: Filter 2.5

7 Reconfiguration Page 7 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 (Communication & Filtering) Board C1 (Communication & Combining) FPGA Reconfiguration Process X X X X X Due to these interruptions it is not possible, to use this setup for online reconfiguration!

8 Online Reconfiguration Page 8 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 (Communication & Filtering) Board C1 (Communication & Combining) FPGA

9 Online Reconfiguration Page 9 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 Board C1 (Communication & Combining) FPGA / ASIC Bridge FPGA Worker Communication Filtering

10 Online Reconfiguration Page 10 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 Board C1 (Communication & Combining) FPGA / ASIC Bridge FPGA Worker Communication X X Reconfiguration Process

11 Online Reconfiguration Page 11 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 Board C1 (Communication & Combining) FPGA / ASIC Bridge FPGA Worker Communication Filtering This connection is part of the fixed Board logic and therefore unchangeable.

12 Dynamic Partial Reconfiguration Page 12 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 (Communication & Filtering) Board C1 (Communication & Combining) FPGA

13 Dynamic Partial Reconfiguration Page 13 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 (Communication & Filtering) Board C1 (Communication & Combining) FPGA Bridge Worker

14 Dynamic Partial Reconfiguration Page 14 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 (Communication & Filtering) Board C1 (Communication & Combining) Reconfiguration Process FPGA BridgeWorker X X

15 Dynamic Partial Reconfiguration Page 15 Norbert Abel & Udo Kebschull, KIP Heidelberg FEE 1 (Analog -> Digital) FEE 2 (Analog -> Digital) FEE 3 (Analog -> Digital) FEE 4 (Analog -> Digital) FEE 5 (Analog -> Digital) FEE 6 (Analog -> Digital) Board F1 (Communication & Filtering) Board C1 (Communication & Combining) This is the maximum possible changeability! FPGA BridgeWorker The worker is online reconfigurable. The complete FPGA is offline reconfigurable.

16 Dynamic Partial Reconfiguration Page 16 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA BridgeWorker

17 Dynamic Partial Reconfiguration Page 17 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA WorkerBridge

18 Dynamic Partial Reconfiguration Page 18 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA BridgeWorker 2 Worker 1

19 Dynamic Partial Reconfiguration Page 19 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA BridgeWorker 2 Worker 1 X

20 Dynamic Partial Reconfiguration Page 20 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA BridgeWorker 2 Worker 1

21 DPR Framework Page 21 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA BridgeWorker 2 Worker 1 Worker 3Worker 4

22 DPR Framework Page 22 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA InWorker 2Worker 1 Worker 3 Worker 4 Out

23 Scheduling - Update Page 23 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA In Track Finder 2.3 Worker 2 Track Finder 2.3 Worker 1 Zero Suppression 3.2 Worker 3 Data Compression 1.7 Worker 4 Out

24 Scheduling - Update Page 24 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA In Track Finder 2.3 Worker 2 Track Finder 2.3 Worker 1 Worker 4 Out X Zero Suppression 3.2 Worker 3

25 Scheduling - Update Page 25 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA In Track Finder 2.3 Worker 2 Track Finder 2.3 Worker 1 Data Compression 1.8 Worker 4 Out Zero Suppression 3.2 Worker 3

26 Scenario-Based Scheduling Page 26 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA In Track Finder 2.3 Worker 2 Track Finder 2.3 Worker 1 Track Finder 2.3 Worker 3 Data Compression 1.8 Worker 4 Out New Scenario!

27 Scenario-Based Scheduling Page 27 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA In Worker 2 Worker 1Out X X Data Compression 1.8 Worker 4 Track Finder 2.3 Worker 3

28 Scenario-Based Scheduling Page 28 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA In Track Fitter 3.2 Worker 2 Track Fitter 3.2 Worker 1 Out Data Compression 1.8 Worker 4 Track Finder 2.3 Worker 3

29 Runtime Scheduling Page 29 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA InWorker 2Worker 1 Worker 3 Out Worker 4 Track Finder 3.7 Data Comp 1.8 Track Finder 3.7 Vertex Finder 2.4 Track Finder 3.7

30 Runtime Scheduling Page 30 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA InWorker 2Worker 1 Worker 3 Out Worker 4 Track Finder 3.7 Track Finder 3.7 Track Finder 3.7 Data Comp 1.8 Vertex Finder 2.4

31 Runtime Scheduling Page 31 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA InWorker 2Worker 1 Worker 3 Out Worker 4 Track Finder 3.7 Data Comp 1.8 Track Finder 3.7 Track Finder 3.7 Vertex Finder 2.4

32 Runtime Scheduling Page 32 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA InWorker 2Worker 1 Worker 3 Out Worker 4 Track Finder 3.7 Track Finder 3.7 Track Finder 3.7 Data Comp 1.8 Vertex Finder 2.4

33 Runtime Scheduling Page 33 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA InWorker 2Worker 1 Worker 3 Out Worker 4 Track Finder 3.7 Vertex Finder 2.4 Track Finder 3.7 Track Finder 3.7 Data Comp 1.8

34 Runtime Scheduling Page 34 Norbert Abel & Udo Kebschull, KIP Heidelberg FPGA InOut Data Comp 1.8 Track Finder 3.7 Vertex Finder 2.4 Track Finder 3.7 Track Finder 3.7 Requirements: - Data of absent workers has to be buffered - Scheduler has to be responsive to changing conditions - Reconfiguration overhead has to be as low as possible - Worker interconnections have to be very flexible - Throughput should stay as high as possible This leads to the need of a Reconfiguration Framework

35 Reconfiguration Framework Page 35 Norbert Abel & Udo Kebschull, KIP Heidelberg VHDL Development of the workers and the In & Out modules in VHDL Partitioning of the design in VHDL Implementation of the scheduler Logical implementation of the inter module communication (IMC) Partitioning of the Chip Physical implementation of the IMC Timing Using the conventional tools... Developers have to care about:

36 Reconfiguration Framework Page 36 Norbert Abel & Udo Kebschull, KIP Heidelberg OO & VHDL Development of the workers and the static In & Out modules Predefined scheduler, partitioning and communication matrix Developers just have to care about: Encapsulated Using our DPR-Framework... Framework

37 Reconfiguration Framework Page 37 Norbert Abel & Udo Kebschull, KIP Heidelberg Functionality: - Data of absent workers is buffered - Scheduler is triggered by the buffer levels - The separation of long and short reconfiguration based on object orientation leads to a minimal reconfiguration overhead - Worker interconnections are free programmable - Runtime Scheduling covers Scenario-Based Scheduling as well as Update Scheduling T1 = new TrackFinder3_7(); T2 = new TrackFinder3_7(); T3 = new TrackFinder3_4(); T1.s.connect(T3.a); T2.s.connect(T1.b); while (1) {... if (scn_ch == 1) T1.finish(); V = new VertexFinder();... } FPGA InOut Data Comp 1.8 Track Finder 3.7 Vertex Finder 2.4 Track Finder 3.7 Track Finder 3.7

38 Reconfiguration Framework Page 38 Norbert Abel & Udo Kebschull, KIP Heidelberg Throughput: 22 MB/s with 16 Bit Databus 44 MB/s with 32 Bit Databus 88 MB/s with 64 Bit Databus 176 MB/s with 128 Bit Databus Example: Worker-Size: 534 CLBs 212 kB Worker-Context: 4 BRAMs 10 kB => Delay: Short Reconfiguration: 26µs Long Reconfiguration:530µs FPGA InOut Data Comp 1.8 Track Finder 3.7 Vertex Finder 2.4 Track Finder 3.7 Track Finder 3.7

39 Reconfiguration Process FPGA BridgeWorker X X Summary Page 39 Norbert Abel & Udo Kebschull, KIP Heidelberg High Energy Physic Experiments produce very high data rates => DAQ has to be very performant High Energy Physic Experiments have a very long lifetime => DAQ has to be very flexible ====> Usually reconfigurable FPGAs are used for DAQ There are two kinds of Reconfiguration: - Offline Reconfiguration - Online Reconfiguration Online Reconfiguration often depends on the separation in Bridge & Worker FPGA InOut Data Comp 1.8 Track Finder 3.7 Vertex Finder 2.4 Track Finder 3.7 Track Finder 3.7 DPR makes it possible to place Bridge and (even multiple) Workers on one FPGA But DPR requires a complex toolflow and much know-how Our DPR Framework encapsulates the DPR specific tools and methods =>Developers can use DPR without going in detail with it

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