3 Multiple-Output Minimization Most digital applications require multiple outputs derived from the same input variables.Example: 3 inputs and 2 outputsEach output function could be minimized using K-map and realized independently.The output functions could share one or more product terms (prime implicant) which reduces the total number of gates.XF1YLogic CircuitF2Z
4 Example F1= XZ+YZ’ F2=XY’+YZ’ To find the common terms multiply the two functions (F1.F2)The common terms are : YZ’, XY’ZXYXXYX00011110Z00011110Z264264111111375137511Z11Z1YXYYXZ000111102641113751Z1Y
6 Real-World Logic Design More than 6 inputs -- can’t use Karnaugh mapsDesign correctness more important than gate minimizationUse “higher-level language” to specify logic operationsUse programs to manipulate logic expressions and minimize logic.PALASM, ABEL, CUPL -- developed for PLDsVHDL, Verilog -- developed for ASICs
7 Timing HazardsThe Truth Table determines the Steady State behavior of a Combinational Logic CircuitTransient behavior: - Output could produce glitches (a short pulse) when input variables change. - Glitches occur when the paths between inputs and output have different delays. - Timing Hazards refer to the possibility of having glitches during input transitions.Hazards : - Definitions. - Finding hazards. - Eliminating hazards.
8 DefinitionsStatic Hazards: * Static-1 Hazard : Two input combinations that : - differ in only one variable both produce logic possibly produce Logic 0 glitch during input variable transition * Static-0 Hazard : Two input combinations that differ in only one variable Both produce logic Possibly produce Logic 1 glitch during input variable transitionDynamic hazards: - The output could change more than once during input transitions - Caused by multiple paths with different delays from input to the output11
9 Example F= YZ+XZ’ Delay in each gate is T . Input changes from XYZ=111 to 110XYZYZZ’XZ’FTglitchYFZX
10 Finding Timing hazards using K-map Two-level AND-OR Circuits :Static 0 hazards do not exist in the sum-of products (AND-OR) implementation.Static 1 hazards are possibleThe K-map of the function F in the previous example : - Cell 6 ( 110 ) and cell 7 ( 111 ) are covered in two product termsXYXFaster00011110ZY1264FZ1113751X111ZStatic 1 hazardY
11 Timing hazards in OR-AND circuits Static 1 hazards do not exist in the Product-of sums (Two-level OR-AND) implementation.Static 0 hazards are possibleThe minimal product of F = ( X+Z)(Y+Z’) - Cell 0 ( 000 ) and cell 1 ( 001 ) are covered in two sum terms - Static 0 hazard occurs when inputs switched between 000 to 001FasterXYX00011110XZFZ26411ZY1375111Static 0 hazardY
12 Eliminating Timing Hazards AND-OR Circuit - Add a prime implicant that combines the two inputs that cause static 1 hazard.---->consensus - Cells 6 & 7 are combined : XYThe hazard-free circuit is :XYX00011110ZY1264F111Z113751111ZX11Y
13 Eliminating Timing Hazards OR-AND Circuit - Add a prime implicant that combines the two inputs that cause static 0 hazard.---->consensus - Cells 0 & 1 are combined : X+YThe hazard-free circuit is :XYX00011110Z264X11FZZ1375111YY
14 SummaryA properly designed two-level SOP (AND-OR) circuit has no static-0 hazards. It may have static-1 hazards.A properly designed two-level POS (OR-AND) circuit has no static-1 hazards. It may have static-0 hazards.Dynamic hazards do not occur in a properly designed two-level AND-OR or OR-AND circuit. It may occur in multilevel circuits.A brute-force method of obtaining a hazard-free realization is to use the complete sum or complete product.Hazard analysis and elimination are typically needed in the design of asynchronous sequential circuits.