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ECE 3110: Introduction to Digital Systems Multiple-outputs minimization Timing Hazards.

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Presentation on theme: "ECE 3110: Introduction to Digital Systems Multiple-outputs minimization Timing Hazards."— Presentation transcript:

1 ECE 3110: Introduction to Digital Systems Multiple-outputs minimization Timing Hazards

2 2 Previous… PoS minimization Don’t care values

3 3 Multiple-Output Minimization Most digital applications require multiple outputs derived from the same input variables. Example: 3 inputs and 2 outputs Each output function could be minimized using K-map and realized independently. The output functions could share one or more product terms (prime implicant) which reduces the total number of gates. X Y Z F1 F2 Logic Circuit

4 4 Example u F1= XZ+YZ’ F2=XY’+YZ’ u To find the common terms multiply the two functions (F1.F2) u The common terms are : YZ’, XY’Z XY Z X Z Y XY Z X Z Y XY Z X Z Y

5 5 Example - Logic Diagram Independent realization Minimal realization F1= XZ+YZ’ F2= XY’+YZ’ X Y Z F1 F2 X Y Z F1 F2

6 6 Real-World Logic Design More than 6 inputs -- can’t use Karnaugh maps Design correctness more important than gate minimization  Use “higher-level language” to specify logic operations Use programs to manipulate logic expressions and minimize logic. PALASM, ABEL, CUPL -- developed for PLDs VHDL, Verilog -- developed for ASICs

7 7 Timing Hazards The Truth Table determines the Steady State behavior of a Combinational Logic Circuit Transient behavior: - Output could produce glitches (a short pulse) when input variables change. - Glitches occur when the paths between inputs and output have different delays. - Timing Hazards refer to the possibility of having glitches during input transitions. Hazards : - Definitions. - Finding hazards. - Eliminating hazards.

8 8 Definitions Static Hazards: * Static-1 Hazard : Two input combinations that : - differ in only one variable. - both produce logic 1. - possibly produce Logic 0 glitch during input variable transition * Static-0 Hazard : Two input combinations that - differ in only one variable - Both produce logic 0 - Possibly produce Logic 1 glitch during input variable transition Dynamic hazards: - The output could change more than once during input transitions - Caused by multiple paths with different delays from input to the output

9 9 Example F= YZ+XZ’ Delay in each gate is T. Input changes from XYZ=111 to 110 X Y Z F X Y Z YZ Z’ XZ’ F T glitch

10 10 Finding Timing hazards using K-map Two-level AND-OR Circuits : Static 0 hazards do not exist in the sum-of products (AND-OR) implementation. Static 1 hazards are possible The K-map of the function F in the previous example : - Cell 6 ( 110 ) and cell 7 ( 111 ) are covered in two product terms XY Z X Z Y 0 X Y Z F Faster Static 1 hazard

11 11 Timing hazards in OR-AND circuits Static 1 hazards do not exist in the Product-of sums (Two-level OR- AND) implementation. Static 0 hazards are possible The minimal product of F = ( X+Z)(Y+Z’) - Cell 0 ( 000 ) and cell 1 ( 001 ) are covered in two sum terms - Static 0 hazard occurs when inputs switched between 000 to XY Z X Z Y 0 Y X Z F Faster Static 0 hazard 0 1 0

12 12 Eliminating Timing Hazards AND-OR Circuit - Add a prime implicant that combines the two inputs that cause static 1 hazard.---->consensus - Cells 6 & 7 are combined : XY The hazard-free circuit is : XY Z X Z Y 1 X Y Z F

13 13 Eliminating Timing Hazards OR-AND Circuit - Add a prime implicant that combines the two inputs that cause static 0 hazard.---->consensus - Cells 0 & 1 are combined : X+Y The hazard-free circuit is : XY Z X Z Y 0 Y X Z F

14 14 Summary A properly designed two-level SOP (AND-OR) circuit has no static-0 hazards. It may have static-1 hazards. A properly designed two-level POS (OR-AND) circuit has no static-1 hazards. It may have static-0 hazards. Dynamic hazards do not occur in a properly designed two- level AND-OR or OR-AND circuit. It may occur in multilevel circuits. A brute-force method of obtaining a hazard-free realization is to use the complete sum or complete product. Hazard analysis and elimination are typically needed in the design of asynchronous sequential circuits.


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