1. Project submitted By RAMANA K VINJAMURI VLSI DESIGN ECE 8460 Spring 2003

2. Introduction ALU – Arithmetic Logic Unit Addition Subtraction Logical functions COMPARATOR - Comparing two inputs A<B (SLT) A>B (SGT) A=B (SEQ)

3. Introduction How we developed the Circuit ? Written a code in VHDL. Obtained a gate level circuit diagram. Developed minimum gates combinational logic diagram. Used LASI tool. Constructed the layout. Finally on a 2mm chip.

4. 4-Bit ALU Standard Cells used…. INVF 101 NANF 201 NANF 301 NANF 401 NORF 201 NORF 301 NORF 401 XORF 201 We used a total gates of : 61 Inverters 55 Nand gates 14 Nor gates 7 Xor gates Total number of gates to construct our ALU are : 137

5. Description of functionality S2S1S0CINFUNCTION 0000Comparator 0001Increment A 0010Addition 0011Add with Carry 0100Subtract with borrow 0101Subtraction 0110Decrement A 0111Buffer (Transfer A) 100XLogical OR 101XLogical XOR 110XLogical AND 111XComplement A Select signalsFunctionality

6. Gate level diagram of the 1-Bit ALU

7. Block representation of the 1-Bit ALU

8. Gate level circuit diagram of the 4-Bit ALU

9. Gate level circuit for 4Bit ALU with Comparator

10. Layout of the 4-bit ALU with comparator W/O connections

11. Final Layout of the 4Bit ALU with connections using LASIMX

12. On a 2mm chip

13. Transistor Layout of the 1Bit Adder

14. Transistor Layout of the 1Bit ALU

15. Transistor Layout of the 4-Bit ALU

16. Transistor Layout of the 4-Bit ALU with Comparator

17. Power Dissipation Average current is 1.850mA Voltage is 5v Average power dissipation is 9.25mW Current magnitudeAverage current

18. Propagation Delay Propagation delay is found to be 6ns from input to output

19. Using as a Comparator Given input A as 1111 and B as 0000 and 1111 alternatively as pulses, We can see the SGT is high at B=0000 and low at B=1111 Also when B=1111 SEQ is high.

20. Using as OR function Given A=0101 and B as 1010 We get the output as 1111

21. Using as AND Given A=1011 and B as 1010 We get the output as 1010

22. Using as XOR Given A=1010 and B as 1010 We get the output as 1010

23. Using as a BUFFER Given A as 0001 and got the output as 0001 Given A as 1001 and got the output as 1001

24. As a complement for input A Given A as 0011 and got the output as 1100

25. Using as a Subtractor Subtraction A”1101” and B”0001” we get F=”1100”

26. MOSIS Submission Request new project ID : Request : PROJECT Account : Alpha D-Name: RANA D-Password:service99 P- Name: CHIP P- Password: service Phone: 610-225-3004 Technology : MOSIS Size : 1.56mm2 Pads: 40 Package : DIP40 Quantity: 1 Description: 4BIT ALU Request : END

27. MOSIS Submission Request : SUBMIT ID:542154 P-Password :SERVICE Layout checksum :212565 Layout Format : GDS Top Structure : QCELL Layout : ftp://123.23.456/ravi/rana/qcell Request: END

28. Project Summary Total number of gates : 137 Total chip size is :1.568mm 2 Average current required is : 1.850mA Working voltage is : 5v Power dissipation is : 9.25mW Delay between input and output is : 6ns Maximum clock frequency is : 166.66MHz