1. 1 Design of 4-bit ALU Swathi Dasoju Mahitha Venigalla Advisor: David W.Parent 6 th December 2004

2. 2 Agenda Abstract Introduction –Why –Simple Theory –Back Ground information (Lit Review) Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions

3. 3 Abstract We designed a 4-bit ALU which can drive a load up to 40fF. The arithmetic operations are A+B, A+B’+1, A-1,Transfer A, A+1,A+B+1,A+B’. The logical operations are A XOR B, A AND B, A OR B, NOT A Date should be transferred at clock frequency of 200MHz with.55ns setup and hold times. Our design uses maximum of 15mW of Power and occupies an area of 345x310  m2.

4. 4 Introduction ALU is the fundamental unit of any computing system. It consists of different kinds of logic. Full adder,Subtractor,Transfer Data,Increment, Decrement,D Flip-Flop,Mux,Inverter,NAND,NOR,XOR. The knowledge of how an ALU is designed and how it works is essential for building any advanced logic circuits.

5. 5 B-INPUT LOGIC RC ADDER Arithmetic Unit XORANDOR Logical Unit INVMUX-2 Bank of 12 DFFsMUX-1Bank of 5 DFFs Block Diagram

6. 6 MS1S0Carry InFunctionCarry Out 0000TransferA 0001 A + 1 0010 A + B 0011 A + B + 1 0100 A + B’ 0101 A + B’ +1 0110 A - 1 0111 TransferA 100X A XOR B X 101X A OR B 110XA AND B X 111X NOT A X Function Table A, B = 4 Bit Input, X = don’t care Condition M, S0, S1 = Status Control Pin Depends on Inputs and Function

7. 7 Project Summary ALU is a combinational circuit that performs a set of basic arithmetic and logical operations. The selection lines are used to determine the operation to be performed. Our design uses Ripple Carry Adder to perform addition.

8. 8 Longest Path Calculations PHL 18  Note: All widths are in microns and capacitances in fF 5 ns.277 ns

9. 9 Schematic – Top Level

10. 10 B-Input Logic Arithmetic Unit

11. 11 Logical Unit

12. 12 2 select pin Mux 1select pin Mux

13. 13 Mux based DFF Schematic

14. 14 1 Bit Adder

15. 15 4-bit ALU layout

16. 16 Final DRC and LVS Report

17. 17 Simulation (Arithmetic Unit) M, S1, S0 are set for A+B’ operation. All A’s and B’s are set to 1111.

18. 18 M, S1, S0 are set for XOR operation. All A’s are set to 1111 and B’s are set to 0100. Simulation ( Logical Unit)

19. 19 Power Graph

20. 20 Cost analysis Time spent on each phase of the project Logic design & check- 1 week. Transistor sizing – 2 weeks. Layouts – 1 week. Post Extraction Check – 2 days

21. 21 Conclusions The ALU performs 12 functions at a frequency of 200MHz and can drive up to 40fF load. The layout of a Ripple Carry Adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The delay for this circuit is nC + S, where n is the number of full adders, C is the time required to calculate (delay) an individual carry value, and S is the delay of an individual sum value. For small adders, this delay is not very important, but for 32-bit or 64-bit computations, the delay can become significant.

22. 22 Acknowledgements Thanks to Professor David W.Parent for his guidance Thanks to Cadence Design Systems for facilitating the use of Cadence Tools.