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Princess Sumaya Univ. Computer Engineering Dept. د. بســام كحـالــه Dr. Bassam Kahhaleh

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Princess Sumaya Univ. Computer Engineering Dept. Chapter 4:

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 2 / 56 Micro-Operations A micro-operation is an elementary operation, performed during one clock pulse, on the information stored in one or more registers. R1 ← R1 + R2

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 3 / 56 Computer Organization The organization of a digital computer is best defined by specifying: ●The set of registers it contains and their function ●The sequence of micro-operations performed on the binary information stored in the registers ●The control functions that initiate the sequence of micro-operations

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 4 / 56 Register Designation Whole register Portion of a register One bit in a register

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 5 / 56 Parallel Register Transfer Unconditional R1 ← R2 Conditional P:R1 ← R2 Simultaneous R1 ← R2, R3 ← R2

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 6 / 56 Basic Symbols for Reg. Transfer SymbolDescriptionExamples Capital Letters & Numerals Denotes a registerA, MBR, R3 SubscriptDenotes a bit of a registerA 2, B i Parenthesis ( )Denotes a portion of a registerI(1– 5), MBR(AD) Arrow ←Denotes transfer of informationA ← B Colon :Denotes termination of control functionP: Comma,Separates two micro-operationsA ← B, B ← A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 7 / 56 Serial Register Transfer S: A i ← A i – 1, A 0 ← 0i = 1, 2, 3

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 8 / 56 Bus Transfer

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 9 / 56 Bus Transfer

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 10 / 56 Bus Transfer

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 11 / 56 Bus Transfer

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 12 / 56 Bus Transfer

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 13 / 56 Bus Transfer

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 14 / 56 Memory Transfer MBR ← M M ← MBR

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 15 / 56 Memory Transfer MBR ← M MBR ← M [ R1 ]

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 16 / 56 Micro-Operation Summary SymbolicDescription A ← B Transfer content of register B into register A MAR ← MBR(AD) Transfer content of AD portion of register MBR into MAR A ← Constant Transfer binary (code) constant into register A ABUS ← R1 R2 ← ABUS Transfer content of R1 into bus A and at the same time transfer content of bus A into R2 MAR Memory address register: holds the address of the memory unit MBR Memory buffer register: holds the data transferred in or out of the memory M [ R ] Denotes the memory word specified by the address presently available in register R M Denotes the memory word specified by the address in an implied register MAR MBR ← M Memory read operation M ← MBR Memory write operation

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 17 / 56 Micro-Operation Types Data Transfer Arithmetic Operations Logic Operations Shift Operations

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 18 / 56 Micro-Operation Types Data Transfer Arithmetic OperationsS = A + B Logic Operations Shift Operations

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 19 / 56 Addition S = A + B Time (Propagation) delay = ?

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 20 / 56 Addition S = A + B t = 0 Time (Propagation) delay = ?

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 21 / 56 Addition S = A + B t = Time (Propagation) delay = ?

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 22 / 56 Addition S = A + B t = 2 Time (Propagation) delay = ?

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 23 / 56 Addition S = A + B t = 3 Time (Propagation) delay = ?

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 24 / 56 Addition S = A + B t = 4 Time (Propagation) delay = 4

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 25 / 56 Addition EA ← A + B Flag

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 26 / 56 A ← A – B _ A ← A + ( B + 1 ) Subtraction

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 27 / 56 Increment A ← A + 1

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 28 / 56 Decrement A ← A – 1

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 29 / 56 Arithmetic

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 30 / 56 Arithmetic C 2 C 1 C 0 Function 0 0 0Y = A + B 0 0 1Y = A + B + 1 0 1 0Y = A + B 0 1 1 Y = A – B 1 0 0Y = A 1 0 1Y = A + 1 1 1 0 Y = A – 1 1 1 1Y = A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 31 / 56 Arithmetic C 2 C 1 C 0 Function 0 0 0S = A + B 0 0 1S = A + B + 1 0 1 0S = A + B 0 1 1 S = A – B 1 0 0S = A 1 0 1S = A + 1 1 1 0 S = A – 1 1 1 1S = A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 32 / 56 Micro-Operation Types Data Transfer Arithmetic Operations Logic Operations Shift Operations AND:S = A Λ B OR:S = A V B XOR:S = A B AND:S = A B OR:S = A + B XOR:S = A B

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 33 / 56 Logic

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 34 / 56 Logic

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 35 / 56 Logic C 1 C 0 Function 0 Y = A Λ B 0 1 Y =A V B 1 0 Y = A B 1 Y = A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 36 / 56 Logic C 1 C 0 Function 0 F = A Λ B 0 1 F = A V B 1 0 F = A B 1 F = A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 37 / 56 Micro-Operation Types Data Transfer Arithmetic Operations Logic Operations Shift Operations ●Logical Shift shl A shr A ●Arithmetic Shift ashl A ashr A ●Circular Shift cil A cir A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 38 / 56 Logical & Arithmetic Shift C 1 C 0 Function 0 F = A 0 1F = shr A 1 0F = shl A 1 F = ashr A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 39 / 56 Logical & Arithmetic Shift C 1 C 0 Function 0 F = A 0 1F = shr A 1 0F = shl A 1 F = ashr A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 40 / 56 Logical & Arithmetic Shift C 1 C 0 Function 0 F = A 0 1F = shr A 1 0F = shl A 1 F = ashr A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 41 / 56 Logical & Arithmetic Shift C 1 C 0 Function 0 F = A 0 1F = shr A 1 0F = shl A 1 F = ashr A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 42 / 56 Logical & Arithmetic Shift C 1 C 0 Function 0 F = A 0 1F = shr A 1 0F = shl A 1 F = ashr A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 43 / 56 Logical, Arithmetic, & Circular Shift C2C2 Shift 0Regular 1Circular

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 44 / 56 Logical, Arithmetic, & Circular Shift C 2 C 1 C 0 Function x 0 0F = A 0 0 1F = shr A 0 1 0F = shl A 0 1 1F = ashr A 1 0 1F = cir A 1 1 0F = cil A

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 45 / 56 Arithmetic and Logic Unit (ALU)

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 46 / 56 Homework Chapter 4 ♦ 4-1 ♦ 4-2 ♦ 4-3 ♦ 4-4 ♦ 4-5 ♦ 4-6 ♦ 4-8 ♦ 4-9 ♦ 4-10 ♦ 4-11 ♦ 4-13 ♦ 4-15 ♦ 4-16 ♦ 4-17

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 47 / 56 Homework Mano 4-1Show the block diagram of the hardware that implements the following register transfer statement: yT 2 : R2 ← R1, R1 ← R2

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 48 / 56 Homework 4-2 The outputs of four registers, R 0, R 1, R 2, and R 3, are connected through 4-to-1-line multiplexers to the inputs of a fifth register, R 5. Each register is eight bits long. The required transfers are dictated by four timing variables T 0 through T 3 as follows: T 0 : R5 ← R0 T 1 : R5 ← R1 T 2 : R5 ← R2 T 3 : R5 ← R3 The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register R5.

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 49 / 56 Homework 4-3Represent the following conditional control statement by two register transfer statements with control functions. If (P = 1) then (R1 ← R2) else if (Q = 1) then (R1 ← R3)

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 50 / 56 Homework 4-4What has to be done to the bus system of Fig. 4-3 to be able to transfer information from any register to any other register? Specifically, show the connections that must be included to provide a path from the outputs of register C to the inputs of register A.

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 51 / 56 Homework 4-5Draw a diagram of a bus system similar to the one shown in Fig. 4-3, but use three-state buffers and a decoder instead of the multiplexers. 4-6A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers. a. How many selection inputs are there in each multiplexer? b. What size of multiplexers is needed? c. How many multiplexers are there in the bus?

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 52 / 56 Homework 4-8Draw the block diagram for the hardware that implements the following statements: x + yz: AR ← AR + BR where AR and BR are two n-bit registers and x, y, and z are control variables. Include the logic gates for the control function. (Remember that the symbol + designates an OR operation in a control or Boolean function but that it represents an arithmetic plus in a microoperation.) 4-9Show the hardware that implements the following statement. Include the logic gates for the control function and a block diagram for the binary counter with a count enable input. xyT 0 + T 1 + y’T 2 : AR ← AR + 1

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 53 / 56 Homework 4-10Consider the following register transfer statements for two 4-bit registers R1 and R2. xT: Rl ← R1 + R2 x’T: Rl ← R2 Every time that variable T = 1, either the content of R2 is added to the content of R1 if x = 1, or the content of R2 is transferred to R1 if x = 0. Draw a diagram showing the hardware implementation of the two statements. Use block diagrams for the two 4-bit registers, a 4-bit adder, and a quadruple 2-to-1-line multiplexer that selects the inputs to R1. In the diagram, show how the control variables x and T select the inputs of the multiplexer and the load input of register R1.

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 54 / 56 Homework 4-11Using a 4-bit counter with parallel load and a 4-bit adder, draw a block diagram that shows how to implement the following statements: x: R1 ← R1 + R2 Add R2 to R1 x’y: R1 ← R1 + 1 Increment R1 4-13Design a 4-bit combinational circuit decrementer using four full-adder circuits.

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 55 / 56 Homework 4-15Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. The circuit generates the following four arithmetic operations in conjunction with the input carry C in. Draw the logic diagram for the first two stages. 4-16Derive a combinational circuit that selects and generates any of the 16 logic functions listed in Table 4-5. SC in = 0C in = 1 0D = A + B (add)D = A + 1 (increment) 1D = A – 1 (decrement)D = A + B’ + 1 (subtract)

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Princess Sumaya University 4343 – Computer Organization & Design Computer Engineering Dept. 56 / 56 Homework 4-17Design a digital circuit that performs the four logic operations of exclusive OR, exclusive-NOR, NOR, and NAND. Use two selection variables. Show the logic diagram of one typical stage.

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