1. Logic BIST
Logic BIST

2. Requirements for BIST-able designs
Scanability
connectivity and tracing
data propagation
clocking
No bus conflicts
No X state propagation to observable outputs
Random pattern testability

3. Sources of X states Violation on a TIE-X gate
Violation on a transparent latch
ROMs or RAMs
Violation on a bus
Non-scan cell 1
conflict Z
floating

4. Effect of X propagation to MISR
Every unknown value can double the number of “correct” signatures
Test response
Signature
X00101
0011X X00101
For 32 unknown values there are no signatures
left for fault detection if 32-bit MISR is used !

5. Control of three-state drivers
Avoid using three state drivers
Exactly one driver should be active at any time in normal and test mode T
No test points !
decoder

6. Preferred mux-based implementation

7. X Feedback loops Unknown oscillatory state
X bounding by blocking the output of the loop
Loop cutting by control points 1 1 1 X 1

8. Memory test schemes Black boxing Transparency Bypass Memory block
space compactors can be used on inputs
multiplexing or gating on the output
driven by flip-flops and MTPI
Transparency
Bypass
Memory
block
Test mode

9. Uncontrollable clocks
Test mode D Q D Q
Clock
Make them controllable in test mode!

10. Pseudo-random testing
Though generated deterministically, test vectors have the characteristics of random patterns
Applicable to both combinational and sequential circuits
Fault simulation is required
No test data to store
Tests generated by very simple hardware
Applicable to BIST
Must be supplemented by other techniques if random-pattern-resistant faults occur

11. Random pattern resistance
20% - 40% of faults are typically random pattern resistant
Fault coverage 20 40 60 80
100
The number of test patterns % ?

12. Example of RPR
s-a-0
Only one out of 232 (4 billion) patterns detects the fault

13. Test points - control points
Types of control points
AND - enhance controllability of “0”
OR - enhance controllability of “1”
XOR - balance control of “0” and “1” without reducing observability
Source of stimuli
generator of test patterns - pseudorandom and switching independently
additional scan cells - pseudorandom and switching independently
phase decoder - quasistatic and strongly correlated

14. AND and OR control points
Test mode
Test mode

15. Control points driven by scan
Test mode P R G M I S
Test mode

16. Multiphase test point insertion (MTPI)D 1 1 1 1 C4 C C3 B C2 A
Phase C1 C2 C3 C4 Test A B C D C1
Pattern
counter 4

17. MTPI architecture
Phase decoder
100%
Fault
coverage F0 F1 F2 F3

18. Logic off-limits to control points
Critical paths
Bus “one-hot” encoding logic for buses
Outputs of large drivers
Bounding logic

19. scan chains STUMPS architecture Control T E C O M P A S G N C T R A O

20. Logic BIST architecture - MTPI
... P R G H A S E I F T
Scan + M I S R
Scan
...
MTPI +
...
Clock
Scan
Sen
BIST controller
Hold /Reset
Hold /Reset
Run
Reset
Done

21. Logic BIST architecture - TPI
...
Scan + P R G M I S R
Scan P H A S E I F T R
... +
...
Scan
Sen
BIST controller
Hold /Reset
Hold /Reset
Done
Clock
Reset
Run

22. BIST session ... C P R G M I S R SC 128 128 PC 1 Reset Hold Hold Reset
Scan M I S R
...
Scan
Reset
Hold
Hold
Reset SC
128
128
Sen PC 1
Clock C
Clock
loading
Sen
unloading

23. Simple BIST controller
Sin
Sen
Sout M I S R
Scan P R G
Sen
...
...
Scan
Shift counter
BIST Run
BIST
Done
Pattern counter
hold
Clock
BIST Reset

24. BIST controller and TAP
Sin
Sen
Sout
Scan M I S R P R G
Sen
...
...
Scan
Shift counter
Pattern counter
hold
TAP
Clk Reset Run

25. Boundary scan and BIST Load BIST registers RUNBIST Unload MISR TAP
Application logic
Pattern counter
PRPG / M ISR
Shift counter
TDI
Device ID register BR
Instruction decoder
TDO
Output
buffer
Instruction register
TMS
TAP
TCK
TRST*

26. Signature comparison
External M I S R 1
hardwired comparator
Internal

27. Handling of primary inputs

28. Handling of primary outputs
BIST

29. Logic BIST flow SCAN X-Bound Test Points BIST Controller Synthesis
Gate level netlist
final core netlist
BIST Controller
Synthesis
RTL to
Gates
Time-based
Simulations
RTL for controller
Parallel Pattern
Simulator
Fault coverage
reports
Verilog / VHDL
testbench
PRPG and MISR
values per pattern
Testbench & Test
Vector Generation
Scan chain load/
unload data
ATE
WGL vectors
results

30. Diagnostics - overview
Use bypass mode and conventional ATPG
Different pattern set for ATPG versus diagnostics
Use only MISR values to diagnose fault
Minimal data volume
complex algorithms to isolate failing gates
Must deal with MISR corruption
Hybrid techniques
MISR value is used to identify failing pattern
BYPASS mode unloads subset of failing patterns

31. Diagnostics- hybrid approach
Run pass/fail test
128k patterns
Check
MISR
Identify failing pattern regions
...
8k patterns
Check
MISR
8k patterns
Check
MISR
8k patterns
Check
MISR
Identify individual failing patterns
8k patterns with MISR re-load after each pattern
Unload a subset of failing patterns
Seed PRPG,
apply pattern
unload scan data
Seed PRPG,
apply pattern
unload scan data
Seed PRPG,
apply pattern
unload scan data
...

32. TI Results At-speed test ? BIST pattern count BIST stuck-at grade
ASIC-1
ASIC-1
ASIC-1
ASIC-1
At-speed test ?
BIST pattern count
BIST stuck-at grade
BIST gate overhead
BIST silicon run time
Delta RTL to gates
Fault simulation time
125MHz
65K
96.0%
3.4%
0.1s
0.6h
0.9h
75MHz
262K
95.7%
2.6%
0.6s
3.0h
3.4h
75MHz
262K
95.3%
2.1%
0.9s
6.0h
5.2h
75MHz
262K
95.6%
1.6%
1.2s
13.4h
4.0h

33. Other results ~90K ? 1250K 62.5MHz Size Speed Coverage # patterns
ARM Core
~90K ?
Over 95%
32K
200 ctrl points, 200 observe points
Size
Speed
Coverage
# patterns
Cisco Telecom
Design
1250K
62.5MHz
96.15%
16K
(ITC 2001)
967 ctrl points, 1000 observe points

34. Summary BIST-able design should have
scan
no internal bus conflicts or floating buses
no X states propagating to observable outputs
be random-pattern testable
X states are bounded by test logic
Random pattern testability is improved by control and observe points
ATPG patterns may be used to achieve the highest possible coverage