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NCHUCS1 Scan Chain Reorder Sying-Jyan Wang Department of Computer Science National Chung-Hsing University.

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Presentation on theme: "NCHUCS1 Scan Chain Reorder Sying-Jyan Wang Department of Computer Science National Chung-Hsing University."— Presentation transcript:

1 NCHUCS1 Scan Chain Reorder Sying-Jyan Wang Department of Computer Science National Chung-Hsing University

2 NCHUCS2 Outline  Overview  Scan chain order: does it matter?  Cluster-based reordering for low- power BIST  Experimental results  Future work

3 NCHUCS3 Outline ■ Overview  Scan chain order: does it matter?  Cluster-based reordering for low- power BIST  Experimental results  Future work

4 NCHUCS4 Digital Testing  To detect manufacturing defects  Apply test patterns and observe output responses  Test patterns generated for targeted fault models

5 NCHUCS5 Scenario for Manufacture Test TEST VECTORS MANUFACTURED CIRCUIT COMPARATOR CIRCUIT RESPONSE PASS/FAIL CORRECT RESPONSES … …

6 NCHUCS6 Scan Test (1)  A structural design-for-testability technique  Storage elements are not directly accessible  Scan test provides an easy way for test access Apply test patterns to circuit under test (CUT) Read output responses from CUT

7 NCHUCS7 Scan Test (2)  Sequential circuit FFs are neither controllable nor observable Combinational Logic Primary Input Primary Output F

8 NCHUCS8 Scan Test (3)  Normal signal path: parallel load Combinational Logic Primary Input Primary Output F

9 NCHUCS9 Scan Test (4)  In scan mode: a shift register Combinational Logic Primary Input Primary Output F Scan in (SI) Scan out (SO)

10 NCHUCS10 Scan Test (5)  To enable scan test Each scan cell has two inputs  Normal input  Scan input All scan cells are connected into a shift register (scan chain)  Turn a sequential test into a combinational one Apply test patterns directly Observe test results directly

11 NCHUCS11 Scan Chain  Normally constructed when placement and routing are done  The order does not matter  Find out the shortest scan chain order Traveling salesman problem (TSP) Asymmetric TSP (ATSP)  SI and SO of a scan cell are not at the same location NP-complete

12 NCHUCS12 Outline  Overview ■ Scan chain order: does it matter?  Cluster-based reordering for low- power BIST  Experimental results  Future work

13 NCHUCS13 Scan Test for Stuck-at Faults  Order does not matter As long as we can scan in test patterns and scan out test responses CUT

14 NCHUCS14 Minimum Wirelength Routing  Use a TSP/ATSP solver Slow  Wirelength can be 10x with random order

15 NCHUCS15 Low-Power Testing  A great concern in recent years  Need to reduce signal transitions The source of dynamic power in CMOS Usually the dominant factor  Reorder scan chain to reduce switching activity transitions 1 transition only

16 NCHUCS16 Delay Testing (1)  Require two-pattern tests First pattern: initialization Second pattern: launch transition  Delay test with simple scan chain Broadside  The output response of the 1st pattern are captured in the scan chain and become the 2nd pattern Skewed load  The 2nd pattern is the result of 1-bit shift of the 1st pattern

17 NCHUCS17 Delay Test (2)  Broadside test Eg. Apply v1=(1010), v2=(0100) Combinational Logic Primary Input Primary Output F

18 NCHUCS18 Delay Test (3)  Skewed load Not all test pairs possible  2 n 2 n possible 2-pattern combinations  Only 22 n possible with single scan chain Reorder scan chain to achieve higher fault coverage NOT POSSIBLE!! 0 110

19 NCHUCS19 Hold Time Violation  Not enough propagation delay between adjacent flip-flops in a sequential circuit Double latching  Possible solution Reorder scan cells to introduce extra delay

20 NCHUCS20 Outline  Overview  Scan chain order: does it matter? ■ Cluster-based reordering for lower-power BIST  Experimental results  Future work

21 NCHUCS21 Overview  Goal: Reduce BIST power  Approach Include a smoother to reduce switching activity in test pattern generator (TPG) Use scan chain reordering to recover lost fault coverage  Simple reordering algorithm  Wirelength should not increase too much

22 NCHUCS22 Overall Architecture Internal scan chain CUT ORA PRPGSmoother TPG Internal scan chain 1 Internal scan chain 2 Internal scan chain k ORAORA PRPGPRPG Smoother PhaseshifterPhaseshifter Single scan chain multiple scan chain

23 NCHUCS23 Smoother 0/1 1/0 0/0 1/0 0/0 1/ S n/2–1 S0S0 0/1 1/1 0/1 S n–1 S n/ /1 0/0 1/0 0/0 1/0 S1S1 0/1 1/1 S3S3 0/1 S0S0 S2S2 1/0 0/0 1/0 S1S1 S0S0 0/0 1/0 S3S3 S2S2 0/0 1/0 0/1 1/1 S5S5 S4S4 0/1 1/1 S7S7 S6S6 0/1 1/1 n-state smoother 4-state (2bit) smoother 8-state (3bit) smoother

24 NCHUCS24 A Simple Implementation of the n-state smother C Divide-by-n/2 Up-Down Counter T u d  q q  C0C0 in

25 NCHUCS25 Estimation of Power Reduction  Probability of signal transition of an n-state smoother Compute from Markov chain model  Estimation of dynamic power 2-bit (4-state ) smoother: 1/3 3-bit (8-state) smoother: 1/10

26 NCHUCS26 Fault Coverage bit smoother3-bit smoother PRPG  Smoothed patterns are less random May create repeated patterns and reduce fault coverage Required test cube: xxxxx01xxxxxxxx NO MATCH! Reorder scan chain: xxxxx0x1xxxxxxx MATCH 2-bit smoother

27 NCHUCS27 Cluster-Based Scan Chain Reorder  Layout surface divided into clusters  Reorder limited in single cluster  Snake-like global routing Single scan chain Multiple scan chains

28 NCHUCS28 Example  Routing s scan cells 1 cluster 256 clustersSilicon Ensemble

29 NCHUCS29 Optimal Cluster Size  Is there an optimal cluster size?  Observation Large clusters--long vertical connection Small clusters--more horizontal crossings  How to find optimal cluster size Find an expression of total wirelength Take its derivative with respect to cluster size c

30 NCHUCS30 Estimate Wirelength in a Cluster (1)  Two types of order Random order Sorted according to x-cooridnate sc 1 sc 2 sc 4 sc 3 sc 5 CL 1 CL 2 sc 1 sc 2 sc 3 CL 1

31 NCHUCS31 Estimate Wirelength in a Cluster (2)  How to estimate the distance between two cells Manhattan distance Horizontal and vertical distances are independent Assuming cells are randomly distributed w (0, 0) h sc 1 (X 1, Y 1 ) sc 2 (X 2, Y 2 )

32 NCHUCS32 Estimate Wirelength in a Cluster (3)  Expected vertical distance between two cells  Expected horizontal distance between two cells Random order: w/3 Sorted order  Summation of all horizontal distances: w

33 NCHUCS33 Estimate Wirelength in a Cluster (4)  Random order N: # cells, c 2 : #clusters  Sorted order

34 NCHUCS34 Optimal Number of Clusters (1)  Random order Assuming H  W, N/c 2  1  Sorted order Assuming H  W, N/c 2  3

35 NCHUCS35 Optimal Number of Clusters (2)  Reordering algorithm Larger clusters give better results Almost no reordering when N/c 2  1 Choose sorted order if no special order is preferred  Optimal cluster size 2  N/c 2  3

36 NCHUCS36 Outline  Overview  Scan chain order: does it matter?  Cluster-based reordering for low- power BIST ■ Experimental results  Future work

37 NCHUCS37 Experimental Results — Wire Length (1)  2-bit smoother

38 NCHUCS38 Experimental Results — Wire Length (2)  3-bit smoother

39 NCHUCS39 Experimental Results — Fault Coverage (1)  2-bit smoother

40 NCHUCS40 Experimental Results — Fault Coverage (2)  3-bit smoother

41 NCHUCS41 Optimal Number of Cells per Cluster CircuitWL (mm) -- SE #cluster#cells/cluster2-bit smoother3-bit smoother GSWL (mm)Red (%)GSWL (mm)Red (%) S S S S S S S S S S S SE: Silicon Ensemble

42 NCHUCS42 Test Efficienct CircuitTL Test Efficiency (%) Markov Source BIST LFSR2-bit smoother3-bit smoother SEOptimal ClusterSEOptimal Cluster S S S S S Average

43 NCHUCS43 Comparison of Average Power Circuit#scan cells TLFC (%) LFSR 2-bit smoother*3-bit smoother*LT-RTPG  (k=3) FC (%) SE FC (%) Opt. cluster AP Red (%) FC (%) SE FC (%) Opt. cluster AP Red (%) FC (%)AP Red (%) S S S S S S S S S S S Average *Full scan;  : only state vectors are scanned

44 NCHUCS44 Peak Power  Capture-cycle power is not reduced  Still provide some improvement Circuit PP Red (%) 2-bit smoother3-bit smoother S S S S S S Average

45 NCHUCS45 Outline  Overview  Scan chain order: does it matter?  Cluster-based reordering for low- power BIST  Experimental results ■ Future work

46 NCHUCS46 Conclusion  Scan chain reorder is very effect to deal with Test power Scan-based delay test Fault coverage in BIST  Need to consider Physical design infromation

47 NCHUCS47 Future Work  Fast reordering algorithm for delay test  Integrate reordering algorithm, considering Test power Delay test coverage Wire length Other issues

48 NCHUCS48 THE END Thank You!


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