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XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 4 December 2008 Martin Postranecky Matt Warren, Matthew Wing.

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Presentation on theme: "XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 4 December 2008 Martin Postranecky Matt Warren, Matthew Wing."— Presentation transcript:

1 XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 4 December 2008 Martin Postranecky Matt Warren, Matthew Wing

2 2 4 Dec 2008C+C Detector Unit Event Builder Farm Readout Crate C+C Crate Timing Receiver Crate Proc- essor C+C Master C+C Slave Train Builder Crate Proc- essor Train Builder PC Switch Machine Storage Controls TCP/IP Network Train Builder Detector Unit Detector Unit 64k Pixel Unit C+C Slave XFEL 2D Pixel DAQ Overview

3 3 4 Dec 2008C+C 1) To receive, process and store Timing Signals from TR ( Timing Receiver ) in same crate : - 5 MHz Bunch CLOCK - Bunch train TRIGGER - Event Number = TRAIN ID - BUNCH PATTERN or Bunch PATTERN ID 2) To receive BUNCH VETO from Veto Hardware 3) To receive STATUS / ERROR ( and possibly Busy ?? ) from each FEE 4) To distribute to each FEE three fast lines : MHz un-interrupted clock, phase-locked to 5 MHz Bunch Clock - START pulse, followed by TRAIN ID, followed by PATTERN ID, followed by STOP signal - BUNCH VETO signal 5) To process any BUSY information from crate controller to stop the following START pulse 6) To generate all Timing Signals in Stand-Alone mode without TR 7) To synchronise to other light sources Timing Systems, i.e. to accept external CLOCK and possibly TRIGGER at different frequencies 8) To provide diagnostic and visual indication of CLOCK, TRIGGER, etc. performance and presence / absence of any FEE C+C HARDWARE : REQUIREMENTS

4 4 4 Dec 2008C+C t1 T1 T2 T1+T2 5 MHz clock in TRIGGER in 100 MHz clock out TRIGGER out VETO out D2 D1 VETO in INPUTS AND OUTPUTS – TIMING RELATIONSHIP

5 5 4 Dec 2008C+C μ TCA Crate Timing Receiver Crate Processor 100 MHz Clock Start/Info/Stop Bunch Veto FEE Status C+C Master FEE C+C Fanout FEE 5MHz Clock Trigger + Telegram Bunch Veto ? 4 FEE 4 C+C Fanout Slave XFEL Timing Interface Other 1-20MHz? Clock Trig/Data ? Overview

6 6 4 Dec 2008C+C C+C Master Clock : 2 XTAL 5MHz Clock From TR Ext Clock 0 – 20MHz? Prog. Mult/Div 100MHz MPX FEE Clock PLL Mult Local Clock 200MHz Prog. Delay Standalone 100MHz Prog. Delay MPX PLL

7 7 4 Dec 2008C+C C+C Master Trigger + Info Trigger + Telegram From TR FEE Trigger Busy Prog. Delay External Interface Ext. Trigger + Info? Trigger Pulse Train ID Bunch Pattern BPID Clock 100MHz ETrigger Pulse ? SA Trigger Pulse SA Train ID SA Bunch Pattern XFEL Interface Select + Process + Store Standalone Trigger + Info LUT

8 8 4 Dec 2008C+C C+C Slave 100 MHz Clock Start/Info/Stop Bunch Veto FEE Status C+C Master Link Fan-out Sync? Fan-out Prog. Delay FEE C+C Link Fan-in x8 Front-panel? Back-plane? Wireless??? ;-) Crate data interface? Front panel (rear?) space? ? ? ?

9 9 4 Dec 2008C+C 1) TRIGGER Telegram from TR : - same line / different lines for TRIGGER, Train ID, Bunch Pattern ?? - Bunch Pattern or Pattern ID ? ( Pattern ID look-up table on C+C ?? ) - Bunch Pattern or Pattern ID ? ( Pattern ID look-up table on C+C ?? ) 2) FEE feedback line : Status only ( e.g.. Normally floating high, pulled low by FEE when powered ), or will contain information ( e.g.. go high when busy or error ) ?? or will contain information ( e.g.. go high when busy or error ) ?? 3) External clock input at other test sites : - 20 MHz range ?? - Always use internal 100MHz clock or PLL to different clock ?? - Always use internal 100MHz clock or PLL to different clock ?? 4) Bunch Veto signal – how fast / latency ?? 5) Calibration Pattern ?? ( pre-loaded into a memory on C+C ?? ) 6) Veto Disable Pattern ?? 7) 100 MHz clock output : - max. jitter ?? - programmable delay / step size ?? - programmable delay / step size ?? 8) Output Clock / Start/Stop pulses phase relationship : - only adjustable on C+C Master, i.e. same for all FEEs ?? - same cable length for all FEEs ?? - same cable length for all FEEs ?? - or individual delay adjustments on each C+C FanOut => more complex FanOuts ?? - or individual delay adjustments on each C+C FanOut => more complex FanOuts ?? MORE INFORMATION / QUESTIONS -1-

10 10 4 Dec 2008C+C 9) Connection between C+C Master and FanOuts : - on custom backplane all signals / 9) Connection between C+C Master and FanOuts : - on custom backplane all signals / FEE feedbacks only ?? FEE feedbacks only ?? - use single or double FanOut layer ?? - use single or double FanOut layer ?? 10) C+C FanOut cards : - separate power on backplane => not TCA-intelligent cards ?? - separate dumb FanOut cards and crate ?? - separate dumb FanOut cards and crate ?? - on / near detector => fewer cables ?? - on / near detector => fewer cables ?? 11) LVDS connectors : - RJ45 – bulky, 4-pairs only, but can use 2x LEDs - Double-stack RJ45 – availability / height ?? - Double-stack RJ45 – availability / height ?? - HDMI - size / more signal pairs / more grounds/shielding ?? - HDMI - size / more signal pairs / more grounds/shielding ?? - Double stack HDMI - size ?? - Double stack HDMI - size ?? - mini-HDMI ?? - mini-HDMI ?? 12) Is there any C&C System interface to MPS ( Machine Protection System ) ?? MORE INFORMATION / QUESTIONS -2-


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