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XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.

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Presentation on theme: "XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System."— Presentation transcript:

1 XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System

2 2 OUTLINE June meeting at DESY June meeting at DESY C&C Hardware structure C&C Hardware structure C&C Firmware structure C&C Firmware structure Current Status Current Status Outstanding Issues Outstanding Issues Future plans Future plans

3 3 June Meeting at DESY June meeting at DESY on XFEL and Petra3 June meeting at DESY on XFEL and Petra3 – Meeting with K. Rehlichs team The structure for the TR board – capabilities The structure for the TR board – capabilities – Supplied signals XTCA backplane signals – P2P clocks and bussed LVDS signals XTCA backplane signals – P2P clocks and bussed LVDS signals XTCA crate structure – How many boards can be supported XTCA crate structure – How many boards can be supported – Meeting with P. Vetrov DAMC2 card structure – capabilities DAMC2 card structure – capabilities – Designed for XTCA – The FPGA and the clock network – MLVDS transceivers – TCLKA and B reception into the clock network – Driving capability doesnt exist RTM connections – 54 differential pairs + 1 dedicated differential clock line RTM connections – 54 differential pairs + 1 dedicated differential clock line FMC connections – If needed for extra functionality FMC connections – If needed for extra functionality Availability Availability

4 4 June meeting at DESY – Meeting with Petra3 team Petra Bunch Uhr (PBU) unit Petra Bunch Uhr (PBU) unit Interfacing PBU with the TR and CC boards Interfacing PBU with the TR and CC boards – Timing – Start, Bunch Clock, Laser inputs + Spare – Signaling types (NIM/TTL) – Conclusions from the meetings TR card will provide clocks and triggers to CC over the XTCA backplane TR card will provide clocks and triggers to CC over the XTCA backplane – XTCA backplane sufficient for CC functionality Bunch clock (4.5 MHz) and 99 MHz clocks will be provided on low-jitter, P2P lines (TCLKA/B) Bunch clock (4.5 MHz) and 99 MHz clocks will be provided on low-jitter, P2P lines (TCLKA/B) DAMC2 can be used as a base for CC card DAMC2 can be used as a base for CC card A custom RTM can be designed for CC master and slave functionality A custom RTM can be designed for CC master and slave functionality

5 5 CC hardware structure Overall timing crate structure Overall timing crate structure

6 6 CC Hardware Structure Detailed CC connections Crate Layout

7 7 CC Hardware Structure DAMC2 + custom RTM DAMC2 + custom RTM Bunch clock on TCLKA, 99 MHz clock on TCLKB from TR Bunch clock on TCLKA, 99 MHz clock on TCLKB from TR – Jitter <= 100 psec On-board oscillator + PLL for standalone testing On-board oscillator + PLL for standalone testing The CC master/slave (1 DAMC2 + RTM) capable of driving a 1 Mpixel 2D detector (16 channels per RTM) The CC master/slave (1 DAMC2 + RTM) capable of driving a 1 Mpixel 2D detector (16 channels per RTM)

8 8 CC Hardware Structure Bussed LVDS lines utilised on xTCA backplane Bussed LVDS lines utilised on xTCA backplane – From the TR RX17, TX17, RX18, TX18 RX17, TX17, RX18, TX18 – From the CC RX19, TX19, RX20, TX20 RX19, TX19, RX20, TX20 The CC will use the TR to synchronise to the following when used with non-XFEL sources The CC will use the TR to synchronise to the following when used with non-XFEL sources – External Clock – External Trigger – Laser Clock – Spare Telegram data content from TR Telegram data content from TR – Start Train, Train Number, End Train, Bunch Pattern Index, DAQ Ready

9 9 CC Hardware Structure Telegrams are to be sent as a data and strobe/clock pair from the TR Telegrams are to be sent as a data and strobe/clock pair from the TR Planned capability for the CC to generate 99 MHz clock and distribute on TCLKB Planned capability for the CC to generate 99 MHz clock and distribute on TCLKB = Signal Source CC Master TCLKA TCLKB RX17 TX17 RX18 TX18 RX19 TX19 RX20 TX20 Bunch Clock FEE Clock (99MHz) Trig (Start) Telegram Data Telegram Clock Reset Command Veto Status Timing Receiver Ext Clock Ext Trig CC Slave Spare MCH

10 10 CC Firmware Structure C&C firmware structure C&C firmware structure

11 11 Current Status – Just received the XUPV5 development board Virtex 5 LX110T FPGA on board Virtex 5 LX110T FPGA on board Various clock sources Various clock sources Differential and single-ended expansion headers Differential and single-ended expansion headers – Going to use XUPV5 for firmware prototyping Until DAMC2, TR, xTCA crate available Until DAMC2, TR, xTCA crate available – Daughter card designs for initial testing (our firmware and hardware) ready 2 different versions 2 different versions Version A – simple I/O functionality – Transmit/Receive on the same card Version A – simple I/O functionality – Transmit/Receive on the same card – Will provide basic test functionality for FEEs – FPGA generated 99 MHz clock / 1 channel output Version B – simple I/O + standalone clock generation + TR interface Version B – simple I/O + standalone clock generation + TR interface – Will provide the same functionality as DAMC2 + RTM – Limited number of channels (1 proposed) – Production will depend on the availability of DAMC2 / FEE needs

12 12 Current Status – Trying to arrange EDA tool usage with RAL Cadence Allegro design flow Cadence Allegro design flow – Telegram data protocol Suggesting a protocol similar to the FAST commands Suggesting a protocol similar to the FAST commands E.g. Start word + Payload + CRC E.g. Start word + Payload + CRC Daughter card designs Daughter card designs Version A Version A Suitable for basic testing FEE functionality Suitable for basic testing FEE functionality - 1 channel output only - 1 channel output only - Clock not in spec but close (jitter, freq.) - Trigger generated by firmware - Trigger generated by firmware (external trigger may be possible)

13 13 Current Status C&C firmware C&C firmware – Fast Message Generation – Start and Stop messages

14 14 Outstanding Issues Telegram data protocol should be finalised Telegram data protocol should be finalised Exact type of inputs to the TR – standard signals to the CC for non-XFEL sources Exact type of inputs to the TR – standard signals to the CC for non-XFEL sources Next version of DAMC2 – changes to TCLKA/B according to CC requirements Next version of DAMC2 – changes to TCLKA/B according to CC requirements – Bi-directional TCLKA/B RTM design considerations RTM design considerations – Specs needed – Size, connector etc. – How to support IPMI – Power supply circuitry – Any other DAMC2 availability and FEE requirements DAMC2 availability and FEE requirements – Will determine the development of either RTM or daughter card B

15 15 Future Plans – Getting the daughter card ready – Firmware development – Initial in-house testing – Expecting DAMC2 – Getting RTM specs – RTM design

16 16 Schedule Daughter card A schematic capture, layout Daughter card A schematic capture, layout Daughter card A production Daughter card A production Firmware development Firmware development Initial tests with the development platform Initial tests with the development platform RTM design/schematic capture RTM design/schematic capture RTM layout RTM layout Tests with the DAMC2 + RTM Tests with the DAMC2 + RTM September 2010 September - October 2010 October 2010 Depends on DAMC2 + crate availability – otherwise daughter card B development October 2010 October – November 2010 November – December 2010 Supplying for FEE testing?

17 17 A -1 RJ J1 0R Shield IDC-1/A RJ J2 0R Shield X-TAL MHz : 2 J3 ( Optional ) RJ45 Start / Reset Veto Status Clock T.R. Clock In Ext. Veto In T.R. Start In Force X-Tal U1 U3 U2 U4U5 U6 U8 U7 U14+U15 U13 U12 U11 SW-1 A-C Coupler U9+U10 DS90LV001 DS90LV027A 2x DS90LV001 DS90LV048A 74LVT74 EuroQuartz XOPL91050UCTA ICS527R-01LF Mult. PLL ICS581G-02LF MUX-PLL Clk-4 Clk-3 Clk-2 In-A In-B Delay Clk-2 Clk-1 U16 99MHz 4.51MHz +3v3

18 18 A-2

19 19 A-3


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