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XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,

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Presentation on theme: "XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,"— Presentation transcript:

1 XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,

2 2 11 May 2010C+C DS90LV001 4k7 100R 2k2 100R 4k7 LVDS output +ve LVDS TEST OUTPUT -ve LVDS TEST OUTPUT DS90LV pF 2 7 U U SK16 SK26 SK15 SK U CLK IN A-C Coupling & Latching Test Circuit -1-

3 3 11 May 2010C+C 100 MHz clock 1= IN+ 2= IN- 3= OUT+ latched 4= OUT- latched

4 4 11 May 2010C+C Paused Signal LONG PAUSE 3= OUT+ latched 4= OUT- latched

5 5 11 May 2010C+C Starting Signal STARTINGS IGNAL 3= OUT+ latched 4= OUT- latched

6 6 11 May 2010C+C Pseudo-Random Signal PSEUDO- RANDOM 1= TTL IN 2= OUT+ latched 3= OUT- latched

7 7 11 May 2010C+C PSEUDO- RANDOM START 1= LVTTL IN 2= OUT+ latched 3= OUT- latched Pseudo-Random Signal - Start

8 8 11 May 2010C+C DS90LV001 4k7 100R 2k2 100R 4k7 +ve LVDS TEST OUTPUT -ve LVDS TEST OUTPUT DS90LV pF EN U1 3 6 EN U k +3v3 Pin n A-C Coupling & Latching Test Circuit -2- RJ DS90LV028 DS90LV U U4 6 5m CAT5 cable

9 9 11 May 2010C+C National DS90LV Mbps LVDS Buffer800 Mbps LVDS Buffer Diff. Delay = 1.4ns typ.Diff. Delay = 1.4ns typ. Part-to-Part Skew = 0ps typ. / 60ps max. ( for same Vcc & temp. )Part-to-Part Skew = 0ps typ. / 60ps max. ( for same Vcc & temp. ) Fall / Rise Time = 310ps typ.Fall / Rise Time = 310ps typ. Peak-to-Peak Data Jitter = 100ps typ.Peak-to-Peak Data Jitter = 100ps typ.

10 10 11 May 2010C+C Current Tests Differential LVDS Pseudo-random signal from FPGA Development Board ( using 100 MHz clock ) 5 m of CAT5-type cable with RJ45 A-C coupling & latching test circuit -2- FPGA Development Board Differential LVDS Test Output fed back to FPGA Development Board Compare and log errors

11 11 11 May 2010C+C Future Plans Finish testing AC-coupling & Latching test circuit -2-Finish testing AC-coupling & Latching test circuit -2- Yes / No decision on balanced signals ( Manchester coding )Yes / No decision on balanced signals ( Manchester coding ) ~2 weeks Final FPGA selection ( PLL, Delays )Final FPGA selection ( PLL, Delays ) Finalise Circuit Design of C&C prototype boardFinalise Circuit Design of C&C prototype board ~ July 2010 Prototype board selection ( DESY ? / RAL ? )Prototype board selection ( DESY ? / RAL ? ) Schematic entry & layout ( RAL )Schematic entry & layout ( RAL ) ~ August - September 2010 C&C Prototype Mk.1 manufactureC&C Prototype Mk.1 manufacture ~ October 2010

12 12 11 May 2010C+C Fanout 8 TCP/ IP Local AMC Control To FEE FPGA TR / Machine etc. Signals or inputs from C&C Master Outputs to Fanouts Single Integrated Prototype Card Master PLL etc

13 13 11 May 2010C+C End…..

14 14 11 May 2010C+C μ TCA Crate Timing Receiver Crate Processor MHz Clock Start/Info/Stop Bunch Veto FEE Status C+C Master FEE C+C Fanout FEE MHz Clk Trigger + Telegram ID Bunch Veto 4 FEE 4 C+C Fanout Slave XFEL Timing Interface Other 1-20MHz? Clock Trig/Data Overview MINIMUM FANOUT REQUIREMENTS : 16 + Fanouts, expandable 3x Outputs ( diff. LVDS, STP/UTP ) 1x Input ( single line, level only )


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