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New Corporate Identity Poster Design Cavendish Laboratory, Department of Physics, University of Cambridge Maurice Goodrick, Richard Shaw, Dave Robinson.

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Presentation on theme: "New Corporate Identity Poster Design Cavendish Laboratory, Department of Physics, University of Cambridge Maurice Goodrick, Richard Shaw, Dave Robinson."— Presentation transcript:

1 New Corporate Identity Poster Design Cavendish Laboratory, Department of Physics, University of Cambridge Maurice Goodrick, Richard Shaw, Dave Robinson Department of Physics and Astronomy, University College London Martin Postranecky, Matthew Warren Poster Number 126 Topical Workshop on Electronics for Particle Physics ( TWEPP-2011 ) Vienna, Austria 26 to 30 Sept Digital Atlas Vme Electronics - DAVE - Module DAVE Module ATLAS-SCT have developed a new ATLAS trigger card, 'Digital Atlas Vme Electronics' ( "DAVE" ) The unit was designed to provide a versatile array of interface and logic resources, including a large FPGA and NIM signalling Interfaces to both VME bus and USB hosts Originally planned as replacement for ATLAS-SCT stand-alone trigger & veto logic NIM crate Many more generic features added to the design Re-used ATLAS CTP firmware to exactly duplicate ATLAS running condition Random trigger, simple and complex deadtime, ECR, BCR, etc. are being generated to give exactly the same conditions in standalone running as experienced in combined runs DAVE card thus evolved into a powerful and flexible logic module Potentially useful to all ATLAS subsystems as well as for other non-ATLAS users ( FPGA with NIM I/O, programmable delays ) Firmware is developed in a modular fashion allowing code contributions from interested users Requirements for CTP-like triggers have been implemented Further development will aim to provide ECR generation, source/sink RAM, trigger history and trigger type generation IN TTL/NIM Sel. CLK-IN ECL/NIM Sel. CLK-OUT ECL/NIM Sel. OUT TTL/NIM Sel. Red LED FPGA Prog. Xilinx PROM Prog. FPGA Switch GSI 18x4Mb SRAM Ext. 5V/3A Conn. Spartan3E FPGA Clock MUX/PLL VME Base Address A A 7x Supply Monitor Red LED 3x Supply OK MHz XTAL Osc. VME J2 Clk+4 Delay Lines VME J1 Blue LED 4x Supply OK Set Serial No. SER SIL JTAG for FPGA USB Reset Switch Set Mod. Record MR Debug & Download DIL for USB MCU 40-pin DIL HEADER 3x LEDs NIM ECL 12x LEDs SHIFT REG. 2 CLKIN0 IN0 IN2 IN6 IN4 CLKIN1 CLKOUT0 OUT0 OUT2 OUT6 OUT4 CLKOUT1 SW NIM ECL NIM TTL NIM TTL HEX SELECT 16-pin AUX. CONNECTOR USB J-TAG X-TAL MHz MPX PLL :2 40/80MHz select CLK Master DELAY 4x Slave DELAYS4 4 4 CLKIN select FPGA & PROM ( incl. 2x diff. pairs 2V5 LVDS ) SW SERIAL NO. MOD. RECORD SW pin DIL BREAK-OUT HEADER (incl. 4x diff. pairs 2V5 LVDS ) 6x POWER 2x GND pins 32 EXT. +5V IN FUSES +3V3 +2V5 +1V8 +1V2 -5V -2V 6x DC-DC VME J1 VME J2 +5V Buffers VME BASE ADDRESS A Data 4Mbx18 SRAM Address MP-UCL, 18 August x LEMO-00 Buffers All POWER Monitor 8 7 2x LEDs SHIFT REG. Xilinx Spartan3e XC3S1600E-5FGG400C 7 6x FUSES 4 USB MCU ATLAS SCT Debug & Download DIL for USB MCU Ext. +5V / 3A Power Conn. CLK-IN 2x LEMOs 00 Global Reset Switch ( FPGA, MCU ) 4-pin USBAUX. DIL 16x I/Os FPGA JTAG Prog. MODE Hex Switch. 3x STATUS LEDs ( Programmable ) 3x4 LEDs ( Programm. ) Programm. Reset Switch CLK-OUT 2x LEMOs 00 DATA-IN 8x LEMOs 00 DATA-OUT 8x LEMOs pin DIL HEADER VME J1 VME J2 FOR MORE INFORMATION SEE : https://twiki.cern.ch/twiki/bin/viewauth/Atlas/DAVEUserGuide UNIVERSITY OF CAMBRIDGE CTP-like Trigger Module Input Enable Sync Output Enable Map ECR Gen Orbit Gen Fine Delays Mask/ GateDead-time SRAM Random Trig VME/USB Interface On-Board FPGA LEMO I/OLVDS I/OClocks Register Block


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