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μ TCA Crate Timing Receiver Crate Processor 100 MHz Clock Start/Info/Stop Bunch Veto FEE Status C+C Master FEE C+C Fanout Slave FEE 5MHz Clock Trigger + Telegram XFEL 2D Pixel C+C Overview Bunch Veto FEE
C+C Master Clock : 2 XTAL 5MHz Clock From TR Ext Clock 0 – 20MHz? Prog. Mult/Div 100MHz MPX MPX PLL FEE Clock PLL Mult Local Clock 200MHz Prog. Delay Standalone 100MHz
C+C Master Trigger + Info Trigger + Telegram From TR FEE Trigger Busy Prog. Delay External Interface Ext. Trigger + Info? Trigger Pulse Train ID Bunch Pattern LUT BPID Clock 100MHz ETrigger Pulse ? SA Trigger Pulse SA Train ID SABPID XFEL Interface Select + Process + Store Standalone Trigger + Info
XFEL 2D Pixel C+C Master/Slave
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 4 December 2008 Martin Postranecky Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL In-kind Review Committee Meeting, 11 May 2009 Parliament British Museum XFEL clock and control system In kind contribution proposal Development and.
XFEL C+C HARDWARE : REQUIREMENTS 1) To receive, process and store Timing Signals from TR ( Timing Receiver ) in same crate : - 5 MHz Bunch CLOCK - Bunch.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 22 October 2009 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, MANNHEIM 02 July 2009 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing.
2 4 Dec 2008C+C Crate Layout CC Master TCLKA TCLKB RX17 TX17 RX18 TX18 RX19 TX19 RX20 TX20 (wired-OR) Bunch Clock FE Clock (99MHz) Trig (Start) EncClock.
XFEL 2D Pixel Clock and Control System. 2 OUTLINE June meeting at DESY June meeting at DESY C&C Hardware structure C&C Hardware structure C&C Firmware.
XFEL Meeting, RAL 20 January 2011 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.
Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous.
XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.
New Corporate Identity Poster Design Department of Physics and Astronomy, University College London Erdem Motuk, Martin Postranecky, Matthew Warren, Matthew.
Thoughts on C&C hardware modularity. Concept Master and Slave will be proper AMC AMC boards will be fairly smart: Micro-controller Small FPGA? –So no.
11 October 2002Matthew Warren - Trigger Board CDR1 Trigger Board CDR Matthew Warren University College London 11 October 2002.
ATLAS SCT/Pixel TIM FDR/PRR28 June 2004 TIM Requirements - John Lane1 ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004 Physics & Astronomy HEP Electronics John.
New Corporate Identity Poster Design Cavendish Laboratory, Department of Physics, University of Cambridge Maurice Goodrick, Richard Shaw, Dave Robinson.
28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky TIM OVERVIEW1 ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004 Physics & Astronomy HEP Electronics.
ZHULANOV Vladimir Budker Institute of Nuclear Physics Novosibirsk, Russia Beijing
ESS Timing System Prototype 2012 Miha Reščič, ICS
Updated HBD FEM Diagram Clock Master Clock fanoutADC Optical out Backplane Crate GTM/Ethernet New Daughter card + DCM Test pulse.
Some features of V1495 Shiuan-Hal,Shiu Everything in this document is not final decision!
Data Acquisition Card for the Large Pixel Detector at the European XFEL 1 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford.
The Clock Distribution inside the CTA Camera Axel Kretzschmann, DESY Zeuthen,
XFEL Meeting, DESY 5 May 2011 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.
Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.
Gueorgui ANTCHEV PH-TOT TOTEM Collaboration Meeting – March TOTEM System in H8 - Overview, Block Diagram and Main Characteristics Applications -
1 Alan Barr, UCL Fixed Frequency Trigger Veto The problem: –Currents in wire bonds in presence of strong magnetic fields –DC current not a problem (small.
Trigger for MEG2: status and plans Donato Nicolo` Pisa (on behalf of the Trigger Group) Lepton Flavor Physics with Most Intense DC Muon Beam Fukuoka, 22.
ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren1 Physics & Astronomy HEP Electronics Matthew Warren John Lane,
01/11/2002SNS Software Final Design Review1 V123S Event Link Encoder, Transmission System and PLL Receiver Thomas M. Kerner (BNL) SNS Global Controls.
A-C Coupler U14+U15 XFEL C-C Test Daughter Card-B, BLOCK DIAGRAM-1. MP-UCL, RJ J1 0R Shield IDC-1/A RJ
Clock and Control Status Matt Warren, on behalf of Martin Postranecky.
DAQ PC CALICE DAQ architecture Detector Unit : ASICs DIF : Detector InterFace connects Generic DAQ and services LDA : Link / Data Aggregator – fanout /
SNS Integrated Control System Timing Clients at SNS DH Thompson Epics Spring 2003.
SNS Integrated Control System SNS Timing Master LA-UR Eric Bjorklund.
The L0 Calorimeter Trigger U. Marconi On behalf of the Bologna Group CSN1, Catania 16/9/02.
UMD Jan Overview Fanout Card (in GLOBAL mode) Fanout Card (in CRATE mode) Fanout Card (in CRATE mode) Fanout Card (in CRATE mode) Unique board for.
3/7/05A. Semenov Batch-by-Batch Intensity Monitor 1 Two-Channel Batch by Batch Intensity Monitor for Main Injector BBI.
FPGA firmware of DC5 FEE. Outline List of issue Data loss issue Command error issue (DCM to FEM) Command lost issue (PC with USB connection to GANDALF)
Pulleys at an Angle. FBD-S m 1 = 100 kg m 2 = 300 kg 30° vivi 0 t10 s θ30° µ0 m1m1 100 kg m2m2 300 kg No Friction.
NOVETO(1) VETO(2) NOVETO(3) VETO(4) NOVETO(5) 3T + Δt fixed decision latency T T LPD latency is fixed = VETO or NOVETO messages arrive with the.
4x4 4 8x LVDS on HDMI ( 8x LVDS on SMA ? ) 8x LVDS on HDMI LVDS on SMA LVTTL on Lemo NIM on Lemo LVDS on SMA 4x LVDS on SMA 4x NIM on Lemo 2x NIM on Lemo.
1.2.7 Trigger A.Nappi TB Nov 11, Digitizers ( ) Functions 25 MHZ 10 bit p.h. + 6bit time digitizers Digital processing Flavor A: p.h.
Jump, Loop, and Call Instructions
Shift Register Application Chapter 22 Subject: Digital System Year: 2009.
NS Training Hardware. System Controller Module.
NIKHEF 27 Feb 2007RELAXd Serial Readout Status1 RELAXd Serial Readout - Status Motherboard MASTER RELAXd Chipboard – SLAVE ADCDACsFlashPower FPGA LatticeSC15.
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