1. Lecture 10: Circuit Families

2. Outline Pseudo-nMOS Logic (Ratioed Logic) Dynamic Logic
Pass Transistor Logic
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3. Introduction What makes a circuit fast?
I = C dV/dt -> tpd  (C/I) DV
low capacitance
high current
small swing
Logical effort is proportional to C/I
pMOS are the enemy!
High capacitance for a given current
Can we take the pMOS capacitance off the input?
Various circuit families try to do this…
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4. EE141
Ratioed Logic

5. EE141
Ratioed Logic

6. EE141
Active Loads

7. Pseudo-nMOS In the old days, nMOS processes had no pMOS
Instead, use pull-up transistor that is always ON
In CMOS, use a pMOS that is always ON
Ratio issue
Make pMOS about ¼ effective strength of pulldown network
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8. Pseudo-nMOS
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9. Pseudo-NMOS VTC
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10. Static Power Dissipation
Pseudo-nMOS Design
Size of PMOS
VOL
Static Power Dissipation
tpLH 4
0.693 V
564 mW
14 ps 2
0.273 V
298 mW
56 ps 1
0.133 V
160 mW
123 ps
0.5
0.064 V
80 mW
268 ps
0.25
0.031 V
41 mW
569 ps
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11. Pseudo-nMOS Gates Design for unit current on output
to compare with unit inverter.
pMOS fights nMOS
Iout = 4I/3 – I/3
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12. Pseudo-nMOS Gates Design for unit current on output
to compare with unit inverter.
pMOS fights nMOS
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13. Pseudo-nMOS Design
Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H
G = 1 * 8/9 = 8/9
F = GBH = 8H/9
P = 1 + (4+8k)/9 = (8k+13)/9
N = 2
D = NF1/N + P =
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14. Pseudo-nMOS Power Pseudo-nMOS draws power whenever Y = 0
Called static power P = IDDVDD
A few mA / gate * 1M gates would be a problem
Explains why nMOS went extinct
Use pseudo-nMOS sparingly for wide NORs
Turn off pMOS when not in use
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15. Ratio Example The chip contains a 32 word x 48 bit ROM
Uses pseudo-nMOS decoder and bitline pullups
On average, one wordline and 24 bitlines are high
Find static power drawn by the ROM
Ion-p = 36 mA, VDD = 1.0 V
Solution:
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16. Pseudo-NMOS Design
Pseudo-nMOS gates will not operate correctly if VOL>VIL of the driven gate.
This is most likely in the SF corner.
Conservative design requires extra weak pMOS.
Another choice is to use replica biasing.
Idea comes from analog design.
Replica biasing allows 1/3 the current ratio rather than the conservative ¼ ratio of earlier.
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17. Replica Biasing
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18. Ganged CMOS
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19. Ganged CMOS A B N1 P1 N2 P2 Y
OFF ON 1 ~0
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20. EE141
Improved Loads

21. Improved Loads
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22. Improved Loads (2) Differential Cascode Voltage Switch Logic (DCVSL)
EE141
Improved Loads (2)
Differential Cascode Voltage Switch Logic (DCVSL)

23. EE141
DCVSL Example

24. EE141
DCVSL Example

25. DCVSL Transient Response
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26. Pass-Transistor Logic
EE141
Pass-Transistor Logic

27. Example: AND Gate
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28. NMOS-Only Logic
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29. EE141
NMOS-Only Switch

30. NMOS Only Logic: Level Restoring Transistor
EE141
NMOS Only Logic: Level Restoring Transistor
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem

31. Restorer Sizing
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32. LEAP LEAn integration with Pass transistors
Get rid of pMOS transistors
Use weak pMOS feedback to pull fully high
Ratio constraint
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33. Complementary Pass Transistor Logic
EE141
Complementary Pass Transistor Logic

34. CPL Complementary Pass-transistor Logic
Dual-rail form of pass transistor logic
Avoids need for ratioed feedback
Optional cross-coupling for rail-to-rail swing
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35. Alternative CPL
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36. Transmission Gate
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37. Resistance of Transmission Gate
EE141
Resistance of Transmission Gate

38. Pass Transistor Circuits
Use pass transistors like switches to do logic
Inputs drive diffusion terminals as well as gates
CMOS + Transmission Gates:
2-input multiplexer
Gates should be restoring
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39. Pass-Transistor Based Multiplexer
EE141
Pass-Transistor Based Multiplexer S S
VDD
GND S
In2
In1 S

40. Transmission Gate XOR
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41. Delay in Transmission Gate Networks
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42. EE141
Delay Optimization

43. Transmission Gate Full Adder
EE141
Transmission Gate Full Adder
Similar delays for sum and carry

44. Other Pass Transistor Families
DPTL (Differential Pass Transistor Logic)
DPL (Double Pass Transistor Logic)
EEPL (Energy Economized Pass Transistor Logic)
PPL (Push-Pull Pass Transistor Logic)
SRPL (Swing Restored Pass Transistor Logic)
DCVSPG (Differential Cascode Voltage Switch with Pass Gate Logic)
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45. Pass Transistor Summary
Researchers investigated pass transistor logic for general purpose applications in the 1990’s
Benefits over static CMOS were small or negative
No longer generally used
However, pass transistors still have a niche in special circuits such as memories where they offer small size and the threshold drops can be managed
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46. Single Clock 2-Phase System
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47. Shift Register
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48. Shift Register
When f = 1, data move through the first transmission gate to the inverter.
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49. Charge Leakage
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50. Charge Leakage
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51. Charge Leakage Both Q and I are nonlinear
Assume that I’s are constant.
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52. Charge Sharing
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53. Charge Sharing We can write The more general case:
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54. EE141
Dynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors

55. Dynamic Gate Two phase operation Precharge (CLK = 0)
EE141
Dynamic Gate
Out
Clk A B C Mp Me
Clk Mp
Out CL
In1
In2
PDN
For class handout
In3
Clk Me
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)

56. Dynamic Gate Two phase operation Precharge (Clk = 0)
EE141
Dynamic Gate
Out
Clk A B C Mp Me
off
Clk Mp on 1
Out CL
((AB)+C)
In1
In2
PDN
For lecture
Evaluate transistor, Me, eliminates static power consumption
In3
Clk Me
off on
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)

57. EE141
Conditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.
Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails.

58. Properties of Dynamic Gates
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Properties of Dynamic Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect the logic levels
Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging CL
CL being lower also contributes to power savings

59. Properties of Dynamic Gates
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Properties of Dynamic Gates
Overall power dissipation usually higher than static CMOS
no static current path ever exists between VDD and GND (including Psc)
no glitching
higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn
low noise margin (NML)
Needs a precharge/evaluate clock

60. Dynamic Logic Dynamic gates uses a clocked pMOS pullup
Two modes: precharge and evaluate
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61. The Foot What if pulldown network is ON during precharge?
Use series evaluation transistor to prevent fight.
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62. Logical Effort
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63. Issues in Dynamic Design 1: Charge Leakage
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Issues in Dynamic Design 1: Charge Leakage
CLK
Clk Mp
Out CL A
leakage sources are reverse-biased diode and the sub-threshold leakage of the NMOS pulldown device.
Charge stored on CL will leak away with time (input in low state during evaluation)
Requires a minimum clock rate - so not good for low performance products such as watches (or when have conditional clocks)
PMOS precharge device also contributes some leakage due to reverse bias diode and subthreshold conduction that, to some extent, offsets the leakage due to the pull down paths.
Evaluate
VOut
Clk Me
Precharge
Leakage sources
Dominant component is subthreshold current

64. Solution to Charge Leakage
EE141
Solution to Charge Leakage
Keeper
Clk Mp
Mkp CL A
Out
During precharge, Out is VDD and inverter out is GND, so keeper is on
During evaluation if PDN is off, the keeper compensates for drained charge due to leakage.
If PDN is on, there is a fight between the PDN and the PUN - circuit is ratioed so PDN wins, eventually
Note Psc during switching period when PDN and keeper are both on simultaneously B
Clk Me
Same approach as level restorer for pass-transistor logic

65. Issues in Dynamic Design 2: Charge Sharing
EE141
Issues in Dynamic Design 2: Charge Sharing
Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
Clk Mp
Out CL A
CA initially discharged and CL fully charged. CA
B=0 CB
Clk Me

66. Charge Sharing Example
EE141
Charge Sharing Example
Clk
Out
CL=50fF A A
Ca=15fF
Out = A xor B xor C
What is the worst case change in voltage on node Out - assume all inputs are low during precharge and all internal capacitances are initially 0V
Worst case is obtained by exposing the maximum amount of internal capacitance to the output node during evaluation. This happens when !A B C or A !B C
30/(30+50) * 2.5 V = 0.94 V so the output drops to = 1.56 V B
Cb=15fF B B !B
Cc=15fF
Cd=10fF C C
Clk

67. Charge Sharing V Clk M Out C A M X C B = M C Clk M DD p L a a b b e
EE141
Charge Sharing V DD
Clk M p
Out C L A M a X C a B = M b C b
Clk M e

68. Solution to Charge Redistribution
EE141
Solution to Charge Redistribution
Clk
Clk Mp
Mkp
Out A B
Clk Me
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

69. Issues in Dynamic Design 3: Backgate Coupling
EE141
Issues in Dynamic Design 3: Backgate Coupling
Clk Mp
Out1 =1
Out2 =0
CL1
CL2 In
A=0
Due to capacitive backgate coupling between the internal and output node of the static gate and the output of the dynamic gate, Out1 voltage reduces
B=0
Clk Me
Dynamic NAND
Static NAND

70. Backgate Coupling Effect
EE141
Backgate Coupling Effect
Out1
Out1 overshoots Vdd (2.5V) due to clock feedthrough
And Out2 never quite makes it to GND
Voltage
Clk
Out2 In
Time, ns

71. Issues in Dynamic Design 4: Clock Feedthrough
Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
Clk Mp
Out CL A
Danger is that signal levels can rise enough above VDD that the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate. B
Clk Me

72. Clock Feedthrough Clock feedthrough Clk Out In1 In2 In3 In & Clk In4
Voltage
In4
Out
Clk
Time, ns
Clock feedthrough

73. Other Effects Capacitive coupling Substrate coupling
EE141
Other Effects
Capacitive coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)

74. Cascading Dynamic Gates
EE141
Cascading Dynamic Gates V
Clk
Clk
Clk Mp Mp
Out2
Out1 In In
Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge.
The second dynamic inverter turns off (PDN) when Out1 reaches VTn.
Setting all inputs of the second gate to 0 during precharge will fix it.
Correct operation is guaranteed (ignoring charge redistribution and leakage) as long as the inputs can only make a single 0 -> 1 transition during the evaluation period
Out1
VTn
Clk
Clk Me Me
Out2 V t
Only 0  1 transitions allowed at inputs!

75. Monotonicity
Dynamic gates require monotonically rising inputs during evaluation
0 -> 0
0 -> 1
1 -> 1
But not 1 -> 0
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76. Monotonicity Woes
But dynamic gates produce monotonically falling outputs during evaluation
Illegal for one dynamic gate to drive another!
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77. Domino Logic Clk Clk Out1 Out2 In1 In4 PDN In2 PDN In5 In3 Clk Clk Mp
EE141
Domino Logic
Clk Mp
Mkp
Clk Mp
Out1
Out2
1  1
1  0
0  0
0  1
In1
Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1
In4
PDN
In2
PDN
In5
In3
Clk Me
Clk Me

78. Domino Gates Follow dynamic stage with inverting static gate
Dynamic / static pair is called domino gate
Produces monotonic outputs
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79. Domino Optimizations
Each domino gate triggers next one, like a string of dominos toppling over
Gates evaluate sequentially but precharge in parallel
Thus evaluation is more critical than precharge
HI-skewed static stages can perform logic
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80. Dual-Rail Domino Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR
Dual-rail domino solves this problem
Takes true and complementary inputs
Produces true and complementary outputs
sig_h
sig_l
Meaning
Precharged 1
‘0’
‘1’
invalid
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81. Example: AND/NAND Given A_h, A_l, B_h, B_l Compute Y_h = AB, Y_l = AB
Pulldown networks are conduction complements
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82. Example: XOR/XNOR Sometimes possible to share transistors
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83. np-CMOS
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84. NORA Logic
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85. NP Domino
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86. Zipper CMOS
The NP-Domino or NORA logic is very susceptible to noise and leakage.
Zipper Domino has the same structure, but the precharge transistors are left slightly ON during evaluation.
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87. Leakage Dynamic node floats high during evaluation
Transistors are leaky (IOFF  0)
Dynamic value will leak away over time
Formerly miliseconds, now nanoseconds
Use keeper to hold dynamic node
Must be weak enough not to fight evaluation
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88. Charge Sharing Dynamic gates suffer from charge sharing
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89. Secondary Precharge Solution: add secondary precharge transistors
Typically need to precharge every other node
Big load capacitance CY helps as well
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90. Noise Sensitivity Dynamic gates are very sensitive to noise
Inputs: VIH  Vtn
Outputs: floating output susceptible noise
Noise sources
Capacitive crosstalk
Charge sharing
Power supply noise
Feedthrough noise
And more!
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91. Power Domino gates have high activity factors
Output evaluates and precharges
If output probability = 0.5, a = 0.5
Output rises and falls on half the cycles
Clocked transistors have a = 1
For a 4 input NAND, aCMOS = 3/16, aDynamic = 1/4
Leads to very high power consumption
However, glitching does not occur in dynamic logic.
The load capacitances are lower.
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92. Completion Detection
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93. Keepers Keeper design is not trivial.
Many alternatives have been suggested.
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94. Conventional Keeper
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95. Weak Keepers
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96. Differential Keeper
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97. Burn-in Conditional Keeper
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98. Adaptive Keeper
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99. Leakage Current Replica Keeper
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100. Footed and Footless Domino
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101. 8-input Domino AND
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102. 8-input Domino AND
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103. MODL
It is often necessary to compute multiple functions where one is a subfunction of the other or shares a subfunction.
One very typical example is the carry in addition:
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104. MODL Carry Chains
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105. MODL Beware of sneak paths. Certain inputs must be mutually exclusive.
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106. Domino Summary Domino logic is attractive for high-speed circuits
1.3 – 2x faster than static CMOS
But many challenges:
Monotonicity, leakage, charge sharing, noise
Widely used in high-performance microprocessors in 1990s when speed was king
Largely displaced by static CMOS now that power is the limiter
Still used in memories for area efficiency
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107. 2-input MUX
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108. Which Logic Style? Ease of design Robustness Area Speed Power
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109. Which Logic Style? Ease of Design Robust-ness Area Speed Power Static
Very good
Bad
Good
Pseudo-nMOS
Average
Very bad
Pass transistor
Difficult
Good (for specific circuits)
average
Dynamic logic
Very difficult
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110. Circuit Pitfalls Threshold drops Ratio failures Charge sharing
Power supply noise
Coupling
Minority carrier injection
Back-gate coupling
Diffusion input noise sensitivity
Race conditions
Delay matching
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111. Circuit Pitfalls Metastability Hot spots Soft errors
Process sensitivity
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112. Threshold Drops
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113. Ratio Failures
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114. Power Supply Noise
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115. Hot Spots
Caused by nonuniform power dissipation even when the overall power consumption is within budget.
Causes variation in delay between gates.
Full-chip temperature simulation is required.
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116. Minority Carrier Injection
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117. Minority Carrier Injection
Sometimes, a node voltage can momentarily exceed power supply voltages.
Then, the drain-body junction becomes forward biased.
Noise tools can identify potential problems.
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118. Diffusion Input Noise Sensitivity
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119. Diffusion Input Noise Sensitivity
Exposed diffusion inputs are particularly sensitive to noise.
Standard cell latches should be built with buffered inputs.
In data paths, one can still utilize exposed diffusion inputs since one knows the structure.
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120. Domino Noise Budgets Charge leakage Charge sharing Capacitive coupling
Back-gate coupling
Minority carrier injection
Power supply noise
Soft errors
Noise feedthrough
Process corner effects
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121. Domino Noise Budgets Source Dynamic Output Dynamic Input
Charge Sharing 10
n/a
Coupling 17 7
Supply Noise 5
Feedthrough Noise
Total
37%
19%
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122. Silicon-on-Insulator Circuit Design
SOI technology has been around for decades as research.
It was adopted by IBM for PowerPC in 1998.
Potential for higher performance and lower power consumption.
Higher manufacturing cost and more complicated circuit design due to unusual transistor behavior.
There is no bulk, but insulator.
Body is floating, thus changes in Vt.
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123. SOI Inverter Cross Section
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124. SOI Process Electron Micrograph
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125. SOI Circuit Design SOI devices are characterized as
Partially Depleted (PD)
Fully Depleted (FD)
In FD SOI, the body is thinner than the channel depletion width, so the body charge is fixed. Thus, the body voltage does not change.
In PD SOI, the body is thicker and its voltage can vary depending on how much charge is present. This varying body voltage changes Vt.
FD SOI is difficult to manufacture.
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126. Charge Paths in SOI Body
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127. Charge Paths
There are two paths through which charge can build up in the body:
Reverse biased drain-to-body (Ddb) and possibly source-to-body (Dsb) junctions.
High-energy carriers causing impact ionization, creating electron-hole pairs. Some electrons are injected into the gate or gate oxide, leaving holes behind.
The charge can exit the body through two paths:
As body voltage increases, Dsb becomes slightly forward biased. Eventually, this cancels the first mechanism above.
A rising gate or drain voltage capacitively couples the body voltage upward, too. This strongly forward biases Dsb junction and charge spills out.
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128. SOI Advantages Lower diffusion capacitance.
Smaller parasitic delay and lower power consumption.
Potential for lower threshold voltages.
Vt is dependent on channel length for bulk CMOS. Thus, worst case conditions are selected in determining Vt. In SOI, variations are smaller, thus smaller Vt can be chosen.
Lower n, hence better subthreshold slope.
n decreases from 1.5 to about 1.2.
SOI is immune to latchup.
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129. SOI Disadvantages PD SOI suffers from history effect.
8% variation in gate delay.
Can be a problem for sensitive analog circuits.
Presence of a parasitic bipolar transistor.
If the source and drain are held high for an extended period of time while the gate is low, the base will float high due to leakage.
If the source is pulled low, the npn turns ON, creating a pulse of current.
This is sometimes called pass-gate leakage.
Self-heating => oxide is an insulator for heat as well.
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130. Parasitic BJT in SOI
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131. Implications for Circuit Styles
SOI is attractive for fast CMOS logic.
Lower delay, lower power consumption.
Standard CMOS design suffers slightly from history effect.
Dynamic circuits suffer from pass-gate leakage. Many precautions must be taken.
Analog circuits suffer from threshold mismatches.
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132. Subthreshold Circuit Design
As discussed earlier, the minimum energy point is at a region where VDD < Vt.
Typically, around 300 mV.
Frequency is in the high kHz or low MHz region.
Vt variations are very important, use large transistors where possible.
Use standard CMOS, but avoid complex gates. Not more complex than NAND3. Due to variations, ON current in one branch may be smaller than OFF current in the series stack.
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133. Pitfalls and Fallacies
Failing to plan for advances in technology
Comparing a well-tuned new circuit to a poor example of engineering practice
Ignoring driver resistance when characterizing pass-transistor circuits.
Reporting only part of the delay of a circuit
Making outrageous claims about performance
Building circuits without adequate verification tools.
Sizing subthreshold circuits for speed
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134. Historical Perspective
Ratioed and dynamic circuits are actually earlier than CMOS.
In an NMOS process, PMOS transistors were not available.
Dynamic gates were proposed in early 1970’s.
Even with CMOS, domino gates were still used for area and power advantages, for example in BELLMAC-32A from Bell Labs.
The world’s first 32-bit microprocessor
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135. Historical Perspective
By the time of Alpha 21264, leakage had become so important that keepers had to be used.
1996, superscalar, out-of-order execution
180 nm Pentium 4 used self-resetting domino.
90 nm Pentium 4 used extraordinarily complex LVS logic. Custom design of 6.8M transistors.
Japanese engineers favored pass transistor logic all through 1990’s.
IBM has always relied on static CMOS.
Hundreds of logic families in academic literature, but very few have found application in industry.
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