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An Efficient Algorithm for Dual-Voltage Design Without Need for Level-Conversion SSST 2012 Mridula Allani Intel Corporation, Austin, TX 78746 (Formerly.

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Presentation on theme: "An Efficient Algorithm for Dual-Voltage Design Without Need for Level-Conversion SSST 2012 Mridula Allani Intel Corporation, Austin, TX 78746 (Formerly."— Presentation transcript:

1 An Efficient Algorithm for Dual-Voltage Design Without Need for Level-Conversion SSST 2012 Mridula Allani Intel Corporation, Austin, TX 78746 (Formerly with Auburn University) Dr. Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 March 12, 2012

2 Outline Motivation Problem statement Background Contributions Algorithm to find V DDL Algorithm to assign V DDL Results Future work References 3/12/2012 2

3 Motivation Current dual voltage designs use 0.7V DD as the lower supply voltage. Algorithms to assign low voltage have exponential or polynomial complexity. Require efficient algorithms that can increase energy savings in large circuits. 3/12/2012 3

4 Problem Statement Develop a linear time algorithm to find an optimal lower voltage V DDL, given a single voltage V DDH without affecting the critical path delay. Develop new algorithms for voltage assignment to gates in dual-V DD design. 3/12/2012 4

5 Background Basic idea: decrease energy consumption without any delay penalty. Done by assigning lower supply voltage to gates on non-critical paths. Different algorithms propose different ways of finding non-critical path gates for lower voltage. 3/12/2012 5

6 Background Authors Kuroda and Hamada say that power reduction ratio is minimum when 0.6V DD ≤ V DDL ≤ 0.7V DD. Authors Chen, et al., Kulkarni, et al., Srivatstava, et al., claim that the optimal value of V DDL for minimizing total power is 50% of V DD. Rule of thumb proposed by Hamada, et. al. says 3/12/2012 6

7 Background CVS Structure [Usami and Horowitz] ECVS Structure [Usami, et. al.] V DDL V DD Level Converter K. Usami and M. Horowitz, “Clustered Voltage Scaling Technique for Low-Power Design," Proceedings of the International Symposium on Low Power Design, pp. 23-26, 1995. K. Usami, et. al.,“Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor," IEEE Journal of Solid-State Circuits, vol. 33, no. 3, pp. 463-472, Mar. 1998. 3/12/2012 7

8 Background Kulkarni, et al. Greedy heuristic based on gate slacks. Uses 0.7V DD or 0.5V DD as V DDL. Includes power and delay overhead of level converters. Sundararajan and Parhi Linear programming based model. Minimizes the power consumption. Includes level converter delay overheads. 3/12/2012 8

9 Background Recent work [Kim and Agrawal]: Assign V DDL to gates with S i ≥S u. Assign V DDL to gates with S l ≤ S i ≤ S u one by one without violating timing or topological constraints. Repeat last two steps across all voltages to find the best V DDL and the corresponding dual-voltage design with the least energy. Ref. K. Kim and V. D. Agrawal, “Dual Voltage Design for Minimum Energy Using Gate Slack,” Proceedings of the IEEE International Conference on Industrial Technology, pp. 419-424, March, 2011. 3/12/2012 9

10 Grouping of gates 45 o line S u = 336.9 ps P G ≥0 3/12/2012 10 ∑(dl i –dh i )≤min{S i }

11 Groups when V DDL = 1.2V 45 o line P G 3/12/2012 11 V DD = 1.2V V DDL = 1.2V T c = 510 ps S u = 0 ps

12 45 o line P G 3/12/2012 12 V DD = 1.2V V DDL = 1.19V T c = 510 ps S u = 14.6 ps Groups when V DDL = 1.19V

13 45 o line S u = 336.9 ps P G 3/12/2012 13 T c = 510 ps Groups when V DDL = 0.49V

14 45 o line P G 3/12/2012 14 V DD = 1.2V V DDL = 0.39V S u = 469ps T c = 510 ps Groups when V DDL = 0.39V

15 Groups when V DDL = 0.1V G 3/12/2012 15 V DD = 1.2V V DDL = 0.1V S u = 510 ps = T c T c = 510 ps P 45 o line

16 Theorems 1. Gates above the 45 o line in the ‘Delay increment versus slack’ plot cannot be assigned lower supply voltage without violating the timing constraint. 2. where β i = dl i /dh i and dl i is the low voltage delay and dh i is the high voltage delay of gate i. The maximum value of β i ; β max, will give us the lower bound on the gate slacks. 3/12/2012 16

17 Theorems 3. Groups within P which satisfy can be assigned lower supply voltage without violating the timing constraint. (where, P’ is a sub-set of P y i = dl i – dh i, dl i = low voltage delay of gate i, dh i = high voltage delay of gate i and S i = slack of the gate i at V DD.) 4. Group with slacks greater than S u, G, can always be assigned the lower supply voltage without causing any topological violations. 3/12/2012 17

18 Algorithm to find V DDL Assume all gates are assigned V DDH initially. Calculate gate slacks. Group gates according to their slacks and delays. 3/12/2012 18

19 Algorithm to find V DDL V DDL = V DDL1, when using no level converter. V DDL = (V DDL1 V DDL2 ) 1/2, when using level converter. 3/12/2012 19

20 Results: V DDL selection algorithm ISCAS ’85 Total gates Without level converters V DDL = V DDL1 V DDL = V DDL2 V DDL = (V DDL1 +V DDL2 )/2 V DDL = (V DDL1 V DDL2 ) 1/2 V DDL (V) Gates in V DDL E sav (%) V DDL (V) Gates in V DDL E sav (%) V DDL (V) Gates in V DDL E sav (%) V DDL (V) Gates in V DDL E sav (%) C4321540.8082.90.8982.30.8482.70.8482.7 C4994930.7611313.71.111414.10.9312310.00.9112911.1 C8803600.4921349.30.7122941.30.622947.70.5822948.8 C13554690.77769.51.111083.40.94766.30.92766.7 C19085840.6022128.41.0022111.60.8022121.90.7722122.3 C26709010.4857053.10.8257033.70.6557044.70.6257046.4 C354012700.521499.50.731497.40.621498.60.611498.7 C531520770.49122049.00.75122636.00.62122043.10.60122044.1 C628824070.55752.51.00770.980.77771.90.73772.0 C728828230.54158244.70.7121238.90.62167243.40.61167243.4 3/12/2012 20

21 Results: Comparison with reported data ISCAS’85 Total gates Without level converters V DDL =V DDL1 V DDL = 0.7V DD = 0.84V V DDL = 0.5V DD = 0.6V V DDL (V) Gates in V DDL E sav (%) Gates in V DDL E sav ( %) Gates in V DDL E sav (%) C4321540.8082.982.783.9 C4994930.7611313.712112.5568.5 C8803600.4921349.322932.422947.7 C13554690.77769.5768.36410.2 C19085840.6022128.422119.322128.4 C26709010.4857053.157032.357047.5 C354012700.521499.51496.01498.8 C531520770.49122049.0124030.5122044.1 C628824070.55752.5771.6752.3 C728828230.54158244.7235942.6167243.9 3/12/2012 21

22 Algorithm to assign V DDL Assume all gates are at V DD initially. Calculate slacks of all gates. Assign V DDL to all gates i whose slacks, S i ≥S u Recalculate slacks. 3/12/2012 22

23 Algorithm to assign V DDL Assign V DDL to a group of gates in P satisfying the condition Recalculate slacks. Are there are any V DDL gates feeding into any V DDH gates or is there any gate with negative slack? 3/12/2012 23

24 Algorithm to assign V DDL If answer to any of the questions is yes, then put the corresponding gate back to V DDH. Recalculate slacks. Repeat previous five steps until we do not have any unprocessed V DDH gate in group P. 3/12/2012 24

25 c880 slack distribution 45 o line S u =336.9 ps P G 3/12/2012 25 V DD = 1.2V V DDL = 0.49V

26 Slack data after V DDL assignment 45 o line S u = 336.9ps P G V DD = 1.2V V DDL = 0.49V 3/12/2012 26

27 ISCAS’85 Total gates V DDL =V DDL1 Determination and assignment SPICE Results ** [Kim and Agrawal] V DDL (V) Gates in V DDL E sav (%) CPU* (s) E single VDD (fJ) E dual VDD ( fJ) E sav (%) CPU (s) C4321540.8082.91.78161.3155.43.7 3.915.8 C4994930.7611313.79.414634277.8 5.9194.4 C8803600.4921349.35.39277.6115.858.3 50.862.1 C13554690.77769.58.75455.2433.14.9 4.3132 C19085840.6022128.411.43496.5378.323.8 19.0247.8 C26709010.4857053.123.49660.3251.561.9 47.8480.7 C354012700.521499.545.441843162012.2 9.61244 C531520770.49122049.0109.472320127245.2 N/R C628824070.55752.5154.94193218693.3 2.66128 C728828230.54158244.7191.042465156236.6 N/R Dual voltage design without level converter Intel Core i5 2.30GHz, 4GB RAM ** 90nm PTM model 3/12/2012 27

28 CPU Time Vs. Number of Gates 3/12/2012 28

29 Future work Accommodate level converter energy overheads. Consider leakage energy reduction. Dual threshold designs. Simultaneous dual supply voltage and dual threshold voltage designs. Include the effects of process variations. 3/12/2012 29

30 References 1. T. Kuroda and M. Hamada, “Low-Power CMOS Digital Design with Dual Embedded Adaptive Power Supplies," IEEE Journal of Solid-State Circuits, vol. 35, no. 4, pp. 652-655, Apr. 2000. 2. M. Hamada, Y. Ootaguro, and T. Kuroda, “Utilizing Surplus Timing for Power Reduction,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 89-92, 2001. 3. C. Chen, A. Srivastava, and M. Sarrafzadeh, “On Gate Level Power Optimization Using Dual-Supply Voltages," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 5, pp. 616-629, Oct. 2001. 4. S. H. Kulkarni, A. N. Srivastava, and D. Sylvester, “A New Algorithm for Improved VDD Assignment in Low Power Dual VDD Systems," in Proceedings of the International Symposium on Low Power Design, pp. 200-205, 2004. 5. A. Srivastava, D. Sylvester, and D. Blaauw, “Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design," Proceedings of the Design, Automation and Test in Europe Conference, pp. 107-118, 2004. 6. K. Kim, Ultra Low Power CMOS Design. PhD thesis, Auburn University, ECE Dept., Auburn, AL, May 2011. 3/12/2012 30

31 References 7. K. Kim and V. D. Agrawal, “Dual Voltage Design for Minimum Energy Using Gate Slack,” in Proceedings of the IEEE International Conference on Industrial Technology, pp. 419-424, Mar. 2011. 8. K. Usami and M. Horowitz, “Clustered Voltage Scaling Technique for Low- Power Design," in Proceedings of the International Symposium on Low Power Design, pp. 23-26, 1995. 9. K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanzawa, M. Ichida, and K. Nogami, “Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor," IEEE Journal of Solid-State Circuits, vol. 33, no. 3, pp. 463-472, Mar. 1998. 10. V. Sundararajan and K. K. Parhi, “Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages," in Proceedings of the 36th Annual Design Automation Conference, pp. 72-75, 1999. 11. M. Allani and V. D. Agrawal, “Level-Converter Free Dual-Voltage Design of Energy Efficient Circuits Using Gate Slack,” Submitted to Design Automation and Test in Europe Conference, March 12-16, 2012. 3/12/2012 31

32 Thank you.

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