1. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 1 Hongshin Jun, Bill Eklow 9/15/2010 BTW10, Fort Collins, CO PCC - Programmable Clock Control for Characterization and Test On chip test clock margining and calibration

2. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 2 Variation Effects with Performance as Technologies Evolve Performance Technology generation Classical Scaling Industry Trend: Nominal Variation With less margin & more variability & modeling becoming more difficult -- we need to be more thorough during debug, verification & testing to avoid margin-driven failures.

3. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 3 Problem Statement  Latest Semiconductor Technology – More Delay (Timing) Faults – Accumulation of marginal parts = board/system level failure – End result = NTFs  ASIC Failure Analysis Challenges  System/Board –Functional Test –Noisy Environment –Isolation is difficult  ATE –Structural Test –Different from Real Env. –More diagnostic capability (shmoo), but tests are not relevant

4. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 4 Problem Statement  Test Performance Characterization Needed – Margin Prediction – Debug (Chip in system) – Data Driven Debug (All About Outliers)  On Chip Clock Control (PCC) – Allows for clock margining at very granular intervals – Can be used in conjunction with current BIST tests – Can be used to help characterize “environmental” effects (power, crosstalk, ….) – Trend data can be used for outlier detection

5. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 5 On-chip Test Clock Generation  Programmable test clock generator (IP)  Clock waveform measurement (IP)  On-chip clock margining responsive to clock measurement (Integration)  For better failure analysis and quality of ASIC

6. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 6 Pulse Selection Method  Delayed clock generator, Pulse PSG, and MUX

7. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 7 Edge Selection Method  Resolution: one buffer delay in the technology

8. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 8 On-chip Timing Measurement Signal Input (SCLK) DMON SCLK EDGEAccumulation

9. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 9 IP Design  IP Includes –Delay Chain, Delay Chain Monitor, and MUX tree  Design Requirements –Linear delay values in delay chain –Balance delay in MUX tree (both data and selection) –Minimize delay variations over PVT –No glitch DMON TDR

10. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 10 IP Design – Clock generation  Dcalmux128  90 nm technology  128-tap delay chain –Support 125MHz or higher –4711 um2 or 1072 gates  Resolution –30ps in Best –70ps in Worst

11. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 11 PCC integrated in Cisco Clock Stopper PLL TDR refClk Normal CS TDR Normal CS TDR 1x 2x  Works with any ATPG/LBIST, JTAG Interface DMON TDR DMON TDR

12. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 12 Characterization

13. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 13 Characterization: Delay Buffers Linear delay values in the delay chain 30ps in BC ~ 90ps in Worst

14. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 14 LBIST Shmoo Correlation 5.904ns 5.750ns 5.0ns 5.173ns 7.656ns 7.750ns

15. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 15 AC Scan Clock Period Stretch  At-speed clock period stretch –The test might be done at slower frequency than at-speed  Need to measure the amount and compensate it  On-chip clock waveform measurement * Graph from “Calibrating clock stretch during AC scan testing”, ITC 2005, by Jeff Rearick, Agilent

16. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 16 Double capture fail at 2.46ns

17. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 17 Burst capture fail at 2.65ns

18. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 18 LBIST Shmoo 2.46 ns2.65 ns 3.47ns (288MHz) -> 190ps Stretch -> 3.66ns (273MHz)

19. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 19 Clock Tree Calibration Mode PLL TDR refClk DMON TDR Normal CS TDR DMON TDR Normal CS TDR 1x 2x  Generate test clock responsive to DMON Same DMON as functional mode

20. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 20 Jitter Insertion: Freq. Stress in EDVT Cs1_pcc_sysClk375 Jitter Best+/- 30*n ps Typical+/- 60*n ps Worst+/- 98*n ps 65n, dcalmux64 How much Jitter? jt_rs[6:0]jt_fs[6:0] 1.33n

21. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 21 Summary  On-chip Clock Margining and Calibration  Margin Characterization & Analysis over End-to-End  Shmoo LBIST / ATPG tests in board/system environment: –Shmoo LBIST for an ASIC while other components are running functionally on board. Can identify “environmental effects”. –Debug ASIC on board with specially generated ATPG (path-delay, bridging, small-delay) patterns on board, to isolate on chip margin defects. –CM can collect LBIST shmoo data without ATE. Supplier can potentially debug the failure without the part. Can possibly be used to identify outlier characteristics as well  PCC Jitter Insertion allows Frequency Stress in EDVT –Works with any functional pattern –Functional BIST

22. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 22

23. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 23 ASICs with PCC ASICBUVendorIPIntegrationTest DanubeDSBUST 90YDone Strider88gDSBUTI 65YDone XgStub2GSBUST 65YDone NileDSBUIBM cu65YDoneOn-Going DopplerDSBUIBM cu65 ,+ On-goingOct 2010 FECRDSBURenesas 65YDoneOn-Going IFEGSBUIBM cu65  On-going AstroSPRTGTI 45On-going FedEx, DHLGSBUIBM cu32

24. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 24 Jitter Insertion: When to insert.. 0101 1x 1/2 start input: Jt_cnt starts when 1/2 is high jt_phase[0] jt_int[31:1] jt_phase_inc[0] 1x1/2 1x 1/2 1x 01 Jt_cnt[0] Jt_cnt[31:1] 01 1x 1/2 0 Jt_cnt[0] Jt_cnt[31:1] 01 1 01 2 01 3 01 4 01 5 01 0 01 1 01 2 01 3 01 4 01 5 Jt_int=5, Jt_phase=0 01 1x 1/2 0 Jt_cnt[0] Jt_cnt[31:1] 01 1 01 0 01 1 01 0 01 1 01 0 01 1 01 0 01 1 01 0 01 1 Jt_int=5, Jt_phase=1 Jt_int=1, Jt_phase=0Jt_int=1, Jt_phase=1 Stress No stress

25. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 25 Nile LBIST Noise Effect ASIC Name:Nile ASIC Vendor:IBM Technology:Cu-65HP # FFs:2.6 million # PLL:4 # Digital IP:0 # High Speed I/O type:SerDes IO (6G&4G), DDR # Embedded Memory326 SRAMs # eDRAMs:17 EDRAMs # External Memories: 3 RLDRAMII, 1 QDR, 1 TCAM4 # Signal Pins:848 # Differential Pins: 136 (96 NWserdes+32 SWserdes+8 clk)

26. © 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 26 References  EDCS-406952: Programmable delay fault test clock generator  EDCS-576749: AC scan clock calibration using PCC  On-chip timing uncertainty measurements on IBM microprocessors, ITC, 2007  Calibrating clock stretch during AC Scan Testing, ITC, 2005