Presentation on theme: "IC TESTING. FUNDAMENTALS OF ELECTRICAL TESTING 1. What Is Electrical Testing? 2. Why Is Electrical Testing Necessary? 3. Anatomy of System-Level Electrical."— Presentation transcript:
FUNDAMENTALS OF ELECTRICAL TESTING 1. What Is Electrical Testing? 2. Why Is Electrical Testing Necessary? 3. Anatomy of System-Level Electrical Testing 4. Fundamentals of Electrical Tests
WHAT IS ELECTRICAL TESTING? A systematic process involves testing at every step to guarantee the functionality and performance of the component before it is committed to the next step and ultimately to the final product.
Anatomy of electrical testing
WHY IS ELECTRICAL TESTING NECESSARY? When faulty chips pass an improperly designed test, they can cause system failures and enormous difficulty in system debugging. Debugging cost increases by about tenfold from chip level to board level, and also from board level to system level. Thus, it is of great importance to detect faults as early as possible.
COST OF TESTING All these combined make for a lot of testing and associated cost. This figure illustrates the product development cycle and approximate distribution of total cost. Design-for-test Test development Product testing These all testing phases can constitute as much as 45% of the total cost.
Fault Types and Models Physical Defects can cause Electrical and Logical Faults: Physical Defects include: – Defects in silicon substrate – Photolithographic defects – Mask contamination and scratches – Process variations and abnormalities – Oxide defects
Electrical and Logical Faults Electrical Faults Shorts (bridging faults) Opens Transistors stuck-on, stuck- open Resistive shorts and opens Excessive change in threshold voltage Excessive steady-state currents Logical Faults Logical stuck-at-0 or stuck- at-1 Slower transition (delay faults) AND-bridging, OR-bridging
PHYSICAL DEFECT IN NOR2 FABRICATION
ELECTRICAL FAULT MODEL
LOGICAL FAULT MODEL
FUNDAMENTALS OF ELECTRICAL TESTS A system-under-test placed within a controlled environment that may include interactions and interfaces with other units. The response is one or more output electronic signals or simply a pass/fail indication. If the measured response matches the expected response (within an allowed margin of error) then the circuit passes the test.
Basic Concept of Electrical Tests
VIDEO OF CHIP TESTING
Test Pattern Generation and Fault Simulation
One possible SSF is characterized by the output of gate 1 being stuck-at logic zero (s-a-0).The fault is activated by applying a logic 1 at the inputs of gate 1. The only direct observation point is at the output of gate 4, the fault effect must be propagated through that gate. This is done by sensitizing a path through gate4, in this case by applying logic zeros to its other inputs. One way to accomplish that is to set (D,E,F,G) (0,0,1,0). So the input test pattern for this fault is (A,B,C,D,E,F,G) (1,0,1,0,0,1,0) and the OUTPUT 1 in the fault-free case, or OUTPUT 0 if the fault exists.