1. Unit 14 Derivation of State Graphs
Fundamentals of Logic Design
By Roth and Kinney

2. 14.1 Design of a Sequence Detector
Clocked Mealy sequential circuit
Circuit has the general form of Figure 14.1
Input: X (string of 0’s and 1’s)
Output: Z=1 only when a specific sequence has been detected.

3. 14.1 (cont.)
Equation 14.1 illustrates Z = 1 when a string of “101” is detected. Note: the system is not reset when the sequence is found many times.

4. 14.1 (cont.)
Assume that the number of flip flops is not known, so we will start with state S0, and continue to S1, S2, etc., as needed.
A state graph will be constructed.
The circuit will initially start at rest.
Figure 14.2—when the first 1 is received we go to state 1. Note that 1/0 indicates X=1 but Z=0.
Figure 14.3—if we receive a 0 after the 1, then we must go to state 2.

5. 14.1 (cont.)
While in state 2, if we receive another 1 then the pattern “101” has been found
Set Z=1 and return to state 1 to look for another sequence of “101”
Figure 14.3 illustrates the partial graph.
Figure 14.4 illustrates the complete graph.

6. 14.1 (cont.) A Table (Table 14-1) can be derived using the graph.
Now the circuit can be derived.
Since there are 3 states, two flip-flops are needed.
A “next state” transition table can be developed, as shown by Table 14.2.

7. 14.1
From the transition table, next-state maps (see page 460 ) can be found.
Flip-Flop inputs (DA and DB) are then derived from the maps—assume that D FFs are used in this example.
This leads to the circuit shown in Figure 14-5.

8. 14.1 (cont.)
Design for a Moore machine is similar to that for a Mealy.
However, the output is written with the states, not with the output between states.
Example similar to Mealy: Z =1 only if 101 has occurred.

9. 14.1 (cont.)
Top of page 461—10 has been sent and we have states 0,1, and 2.
If a 1 input comes next then, 101 has been received and the output must be a 1—this requires state 3 (see 2nd figure on page 461).

10. 14.1 (cont.) Complete the Graph (see Figure 14.6) Table 14-3
100 will reset the circuit to S0.
1010 takes the circuit back to S2.
Table 14-3
State table corresponding to the Moore graph.
Note that there are 4 states and only one column for Z.
Table 14-4 shows the transition table.

11. 14.2 More Complex Design Problems
Two different patterns produce Z=1; “010” and “1001”—see page 463.
State Graph (Mealy)
Start with one of the sequences, then add the other to the state graph.
Figure 14-8 shows the partial graph for “010”.
Figure 14-9 shows the additional graph for “1001”, but Figure is better since we do not have to add the additional state.

12. 14.2 (cont.)
So now Z=1 when the input sequence 010 or 1001 is completed.
NEXT—complete the state graph
If we are in S1, and the input is 0 then we have a 00 sequence –we can stay in S1.
If we are in S2, and the input is a 1 (0 is already taken care of ) and we have a sequence ending in 11—we can go to S4.

13. 14.2 (cont.) NEXT—completing the state graph (cont.)
S3—already has arrows corresponding to 0,1.
S4– If a 1 is received we can stay in s4 and ignore the extra 1 (11 is not part of either sequence (010 or 1001)).
S5-- Already has a 0 input result and a 1 input result.
RESULT—Figure 14-10, page 465.

14. 14.2 (cont.)
Derivation of STATE graph for Moore sequential circuit.—pages

15. 14.3 Guidelines for Construction of State Graphs
1-7, page 467
1) Construct some simple examples
2) Determine under what conditions the circuit should reset.
3) If only one or two sequences lead to nonzero output, construct a partial state graph.

16. 14.3 (cont.)
4)Another way to start is to determine what sequences or groups of sequences must be remembered, and then set up the states accordingly.
5) When adding an arrow, try to use previously defined states, and then add new ones.

17. 14.3 (cont.)
6) Check your graph to make sue there is one and only one path leavin each state for each combination of values of the input variables.
7) When complete, test your graph using the sequences formulated in step 1.

18. 14.3 (cont.) Example 1 Input: X Output: Z
Sequences entered 4 bits at a time.
Z=1, when input sequence “0101” or “1001” is found.
STEP1: test sequences on page 468.
STEP2: Resets after 4 input values.

19. 14.3 (cont.)
Example 1 (cont.)
STEP3: Start with partial state graph is shown (Fig.14-14)
STEP4: Another start: list of states and Sequence Group Received (Fig ).
STEP5: Add Arrows and Labels, to take care of sequences which do not give a 1 output. (Fig )

20. 14.3 (cont.)
Example 1 (cont.)
STEP 6: Check graph to make sure there is one and only one path leaving each state for each combination of values of the input variables.
STEP7: TEST with step 1 sequences.

21. 14.3 (cont.) Example 2 INPUT: X OUTPUTS: Z1, Z2
Z1 =1 , after input “100” has occurred provided that “010” has never occurred.
Z2 =1 , after input “010”.
Fig —partial state graphs
Table 14-5—state description

22. 14.3 (cont.) Example 2 (cont.) Example 3
Fig shows partial and completed state graphs.
Table 14.6 State Table
Example 3
TWO Input: X1 and X2
ONE OUTPUT

23. 14.4 Serial Data Code Conversion
Final Example of STATE Graph Construction
Fig Serial Data Transmission
Fig Coding Schemes

24. 14.5 Alphanumeric State Graph
When a state sequential circuit has several inputs, it is often convenient to label the state graph arcs with alphanumeric input variable names instead of 0’s and 1’s.

25. 14.6 Incompletely Specified State Tables
Sometimes particular input sequences will never occur as inputs; other times the output from a sequential circuit is only observed at certain times rather than at every clock time.
A state table containing such don’t –cares is called an Incompletely Specified State Table.