1. Work in Progress --- Not for Publication 1 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting 2011 ITRS Emerging Research Devices Working Group Face – to – Face Meeting Jim Hutchby – Facilitating San Francisco Marriott Hotel 55 Fourth Street Room – Salon 5 San Francisco, California Sunday July 10, 2011 9:00 a.m. – 6:00 p.m.

2. 2 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting  Hiroyugi AkinagaAIST  Tetsuya AsaiHokkaido U.  Yuji AwanoKeio U.  George BourianoffIntel  Michel BrillouetCEA/LETI  Joe BrewerU. Florida  John CarruthersPSU  Ralph CavinSRC  An ChenGLFOUNDRIES  U-In ChungSamsung  Byung Jin ChoKAIST  Sung Woong ChungHynix  Luigi ColomboTI  Shamik DasMitre  Erik DeBenedictisSNL  Simon Deleonibus LETI  Bob FontanaIBM  Paul FranzonNCSU  Akira FujiwaraNTT  Christian GamratCEA  Mike GarnerIntel  Dan HammerstromPSU  Wilfried HaenschIBM  Tsuyoshi HasegawaNIMS  Shigenori HayashiMatsushita  Dan HerrSRC  Toshiro HiramotoU. Tokyo  Matsuo HidakaISTEK  Jim HutchbySRC  Adrian IonescuEPFL  Kiyoshi KawabataRenesas Tech  Seiichiro KawamuraSelete  Suhwan KimSeoul Nation U  Hyoungjoon KimSamsung  Atsuhiro KinoshitaToshiba  Dae-Hong KoYonsei U.  Hiroshi KotakiSharp  Mark KryderINSIC  Zoran KrivokapicGLOBALFOUNDRIES  Kee-Won KwonSeong Kyun Kwan U.  Jong-Ho LeeHanyang U.  Lou LomeIDA  Hiroshi MizutaU. Southampton  Kwok NgSRC  Fumiyuki NiheiNEC  Ferdinand PeperNICT  Yaw ObengNIST  Dave RobertsNantero  Barry SchechtmanINSIC  Sadas ShankarIntel  Atsushi ShiotaJSR Micro  Satoshi SugaharaTokyo Tech  Shin-ichi TakagiU. Tokyo  Ken UchidaToshiba  Thomas VogelsangRambus  Yasuo WadaToyo U.  Rainer WaserRWTH A  Franz Widdershoven NXP  Jeff WelserNRI/IBM  Philip WongStanford U.  Dirk Wouters IMEC  Kojiro YagamiSony  David YehSRC/TI  Hiroaki YodaToshiba  In-K YooSAIT  Victor ZhirnovSRC Emerging Research Devices Working Group

3. Work in Progress --- Not for Publication 3 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Emerging Research Devices Working Group Meeting Objectives 2011 ITRS ERD Chapter Preparation u Review administrative aspects  Deliverables and revised time line  Chapter outline and page count u Review the Emerging Memory, Logic & Architecture Sections  Table Content (Current & projected tables)  Major device research needs & technical barriers  Key materials scientific and/or technological issues  Thrust, tone & structure of the draft section  Critical Review Section  Review the Difficult Challenges Section  Review Scope and Taxonomy Sections  Review content of the Guiding Principles Section  Decide messages for the Public Presentation

4. Work in Progress --- Not for Publication 4 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting ITRS ERD WG Meeting – July 10, 2011 Agenda 8:30 Light Continental Breakfast 9:00 Welcome and Introductions 9:10Review meeting objectives & agenda Hutchby 9:30 Review status of ERD ChapterHutchby  Deliverables and Timeline  Chapter Organization & Status  Decisions made 9:45Complete Memory, Logic, More-than-Moore, and Architecture, Sections  Table Content (Current & projected tables)  Major Research Needs & Technical Barriers  Thrust, Tone & Structure of the Draft Section 9:45 Logic and Information Processing SectionBourianoff 11:00Break 11:15Memory SectionZhirnov

5. Work in Progress --- Not for Publication 5 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting ITRS ERD WG Meeting – July 10, 2011 Agenda 12:30 Working Lunch 1:15 More-than-MooreBrillouet 1:45 Architecture Section Cavin/Asai 2:30 Review Materials Chapter Related to ERDGarner 3:45Introduce Initial Results of Memory & LogicHutchby Critical Review & BenchmarkingWelser 4:45Review Difficult ChallengesHutchby 5:00Review Scope and Taxonomy SectionsHutchby 5:15 Review Guiding Principles Section Bourianoff 5:30 Decide Messages of ERD Public PresentationHutchby 6:00 Adjourn Meeting

6. Work in Progress --- Not for Publication 6 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Draft ERD Chapter Outline  Scope (1 page)  Difficult Challenges (1)  Taxonomy Chart (1)  Devices  Memory Devices (13)  Logic Devices (15)  More than Moore (5)  Architectures (12)  Critical Assessment (8)  Fundamental Guiding Principles (1)  References (15)  Total Pages (72)

7. Work in Progress --- Not for Publication 7 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting 2011 ERD Working Group Organization ERD FunctionLeader u Chapter Chair – North AmericaHutchby u Chapter Co-chair – Japan ERDUchida u Chapter Co-chair – EuropeIonescu u Chapter Co-chair – Korea ERDChung u MemoryZhirnov u LogicBourianoff u More-than-MooreBrillouet u ArchitectureFranzon u Editorial TeamHutchby, Bourianoff, Brillouet, Franzon, Chung, Garner/Herr, Ionescu, Zhirnov, Uchida u ITRS Liaisons –PIDSNg, Hutchby –FEPColombo –Modeling & SimulationDas/Shankar –MaterialsGarner –MetrologyHerr/Obeng –DesignYeh/Bourianoff –More than MooreBrillouet

8. Work in Progress --- Not for Publication 8 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting 2011 ITRS/ERD Major Deliverables and Timeline ERD Chapter due August 15, 2011 Major Tasks and Time Line  Scope, Difficult Challenges, etc.April 30  Outlines for Memory, Logic, MtM, Arch, Mat’lApril 30  Technology Requirements TablesJuly 1  Tables sent to editorAugust 1  Guiding Principles Section April 30  Draft Text Completed  Memory, Logic, MtM, Architecture, Material June 1  Benchmarking and Critical ReviewJuly 1  Chapter CompletedAug. 15  Chapter FrozenSept. 15 Major Face-to-Face Meetings in 2011  ITRS/ERD Meeting Berlin, GermanyApril 10  ITRS/ERD Meeting at Semicon West (SF, CA)July 10  ITRS/ERD Meeting near Seoul, KoreaDec. 11

9. Work in Progress --- Not for Publication 9 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting 2011 ITRS/ERD Major Deliverables and Timeline ERD Chapter due August 1 15, 2011 Major Tasks and Time Line  Scope, Difficult Challenges, etc.April 30  Outlines for Memory, Logic, MtM, Arch, Mat’lApril 30  Technology Requirements TablesJuly 1  Draft Tables sent to editorAugust 1 June 1  Guiding Principles Section April 30  Draft Text Completed  Memory, Logic, MtM, Architecture, Material June 1  Benchmarking and Critical ReviewJuly 1  Chapter CompletedAug. 15 Aug. 1  Chapter FrozenSept. 15 Major Face-to-Face Meetings in 2011  ITRS/ERD Meeting P, GermanyApril 10  ITRS/ERD Meeting at Semicon West (SF, CA)July 10  ITRS/ERD Meeting near Seoul, KoreaDec. 11

10. Work in Progress --- Not for Publication 10 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting # Decisions Made 2011 1. Memory: ♦ Put Vertical MOSFET in the Memory Section. 2. Logic: ♦ Leave n-channel Ge and InP MOSFETs and p-channel GaSb MOSFETs in ERD/ERM ♦ The Tunnel FET should remain in the main Logic Tables and Section. ♦ Nanowire FET stays in ERD/ERM. ♦ Remove molecular from Logic Section – does not meet criteria ♦ Add MOTT-FET to the Logic Section ♦ Remove SET or move SET to the MtM Section ♦ Keep InP and Ge n-channel and GaSb p-channel MOSFETs in the Logic Section ♦ Add devices from NRI that meet the selection criteria ♦ Do not include Vertical MOSFET in Logic; keep/put in Memory Section. ♦ Change “Collective Spin Wave? to “Spin Wave”. ♦ Logic Working Group is: Shamik (Nanowires), Adrian (Tunnel FET),??(InP, Ge, GaSb), Jeff Welser (NRI Devices added), Jeff Kitun? ♦ Include the Spin Torque Majority Gate. ♦ Keep the Atomic Switch in Logic Tables (corrected Feb. 17, 2011)

11. Work in Progress --- Not for Publication 11 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Decisions Made 2011 More-than-Moore ♦ Architecture issues related to More-than-Moore will be in the MtM Section. ♦ Consider including items related to on-chip technology integration or “Technology Fusion” Architectures: ♦ Add Architectures to the Scope Section ♦ Sequence of Architecture subsections o Memory o Von Neumann o Non Von Neumann ♦ Architecture Working Group: Paul Franzon, Tetsua Asai, Matt Marinella, Lou Lome, Sadas Shankar ( Paul and Asai-san will be the writers and all will be commentators.) ♦ Change Architecture part of Taxonomy Chart. ♦ Harvard versus Morphic architectures New Highlight Section: Create a new Highlight Section as part of the Critical Assessment Section for : ♦ Carbon-based Nanoelectronics, and for ♦ STT-MRAM and Redox RRAM Materials ♦ Develop a table of Devices mapped onto materials and their critical property required to demonstrate the key attribute of the device.

12. Work in Progress --- Not for Publication 12 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting # Action (AI) Items: 2011 1. Add Architectures to the Scope SectionHutchby 2. Consider both “Neumann” and “Beyond Neumann” (or morphic) architectures (Paul Franzon, Tetsua Asai and the Architecture Working Group will explore and develop this approach. Franzon and Asai 3. Should Storage Class Memory drive a new architecture discussion in the Architecture Section? Explore a definition of SCM Zhirnov and Schechtman 4. Explore fitting the SET for ADC application in the MtM Section. The SET is still in active research at NTT in Japan. Brillouet 5. Develop a table of Devices mapped onto materiel and their critical property required to demonstrate the key attribute of the device. Bourianoff Garner and Zhirnov 6. Rename the FeFET to include the Fe-barrier device.Zhirnov 7. Send ITRS URL Link to obtain the PPT files of this meetingHutchby 8. Change “Nanobridge Cantilever” to just “Nanobridge”Zhirnov 9. Talk to Jeff Welser regarding which NRI devices meet our criteria to include them in the ERD Chapter. Bourianoff 10 Consider including items related to on-chip technology integration or “Technology Fusion” Brillouet 11. Change Architecture part of Taxonomy Chart.Hutchby 12, Make the NRI benchmarking methodology available to ERDWelser 13, Prepare a standalone section on benchmarking new devices using new device parameters Welser Bernstein

13. Work in Progress --- Not for Publication 13 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Feedback on 2009 ERD Chapter Overall Comments  Excellent overall readability and balance as a summary  Appropriate level of detail  Scope  Define the terrain covered by performance gains  Define “ultimately scaled CMOS”  Clarify “new information processing paradigm”  Clarify “bulk CMOS”  Difficult Challenges  Clarify the term “bridge a knowledge gap”  Italicize “This development would provide a significant increase in information …”  Give an example of a new application that can be better performed by a new device than by CMOS.  Taxonomy – How useful is this to the reader?  Critical Assessment  Some editorial comments  Define “functional”  Is the term “access resistance” sufficiently general?  Comment on “compared to the existing memory technology” Should it say “compared to existing memory technology scaled to its limit:”?  How can we obtain more votes in the Critical Review?  Include the OPA score in the left column of ERD 14 and 15.

14. Work in Progress --- Not for Publication 14 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Feedback on 2007 ERD Chapter Overall Comments (Held over)  Mission of ERD is not clear cut to universities – clearly state the mission in the introduction.  Need more detailed discussion of key messages and issues between ERD and ERM  Is a Technology Entry being limited by Fundamental Limits or a technologically limited research gap?  ERD needs to maintain a dialog with the Systems Drivers Chapter  Should ERD continue to include a failing Technology Entry?

15. Work in Progress --- Not for Publication 15 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Feedback on 2009 ERD Chapter Emerging Research Memory Devices ♦ Transfers  Expand the scope by including a new section on the “Select Device”, either a diode or transistor  Expand the scope by including Storage Class Memorysuch as Magnetic Packet Memory ( Racetrack)  Move Nanowire Phase Change Memory to the Memory Transition Table and recommend its transition to PIDS as a variant of PCM.  For the time being, keep the Electronics Effects Memory intact as a category for further discussion, with the exception of moving Fe Polarization Memory to the FeFET category and devising a new name to distinguish this from the Fe Capacitor Memory  Add a row in the Memory Table to include an indication of a particular memory suitability for SCM ♦ Other comments  Include optical memory for More-than-Moore?  Need to define (or make a table) a role ( necessary condition) of memory element as an interconnection. Examples ; o For configurable logic using such as CMOL o For Inference Architecture such as Bayesian inference networks

16. Work in Progress --- Not for Publication 16 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Feedback on 2009 ERD Chapter Emerging Research Logic Devices (1/3) ♦ Transfers  III-V Alternate Channel Materials to PIDS/FEP and  Low Dimensional Materials to PIDS/FEP (keep GNR & CNT FETs)  Move Molecular Devices to the Transition Table.  Include Band-to-Band Tunneling Device category in Table 1.  Move RTD out of Table 2 to Transition Table ♦ Other comments (decisions)  Keep the 3 Logic Tables used in 2009 and change “Channel” to “Device” in the first table.  Keep open for more discussion the disposition of vertical MOSFETs – Decide in Dec. Meeting  Put the Tunnel Transistor in the Transition Table for Logic  Add a new Section on More-than-Moore focused on Wireless Devices.  Move the SET to the new More than Moore Section  Move the Negative Capacitive Devices to the Logic Transition Table

17. Work in Progress --- Not for Publication 17 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Feedback on 2009 ERD Chapter Emerging Research Logic Devices (2/3) ♦ Other comments (decisions)  Include the “Mott FET’ in the Logic Tables. (Call it Electronic Phase Change?)  Mention “Excitonic Device” in the Logic Text – put in the Logic Transition Table?  Under Collective Spin Devices include: Spin Wave Device and All Spin Logic  The IRC approved the ERD and ERM to publish the results of the Barza Memory Wor ksho p, but make clear that this is not a selection of a technology  Transfer unconventional FET s, Tri-Gate, FinFET, GAA FETs, to PIDS/FEP ♦ Other comments (under discussion)  In the Logic Transition Table, the IN/OUT entries for Ge FET, Spin MOSFET, Collective Spin Devices, Pseudomorphic, and Nanomagnetic Devices should be move into the Comment column to the right. Entries in the IN/OUT column might better be technical in nature.

18. Work in Progress --- Not for Publication 18 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Feedback on 2009 ERD Chapter Emerging Research Logic Devices (3/3) ♦Other comments (under discussion)  Introduction of energy efficiency criteria? Important  Role of other functionality than digital of beyond CMOS: image processing, analog, RF, etc.  Convergence of beyond CMOS and More than Moore technology entries? MEMS/NEMS already in chapter.  More interaction with emerging architectures needed.

19. Work in Progress --- Not for Publication ERD WG FxF Meeting 4/10/11 Potsdam, Germany19 Backup Slides

20. Work in Progress --- Not for Publication ERD WG FxF Meeting 4/10/11 Potsdam, Germany20 A Taxonomy for Nano Information Processing Technologies New Information Processing Technologies Conventional Scaled CMOS State Variable Device Data Representation Architecture Material SETs Molecular SpintronicsQuantum Scaled CMOS Ferromagnetic Quantum Analog Digital Reconfigurable Morphic Von Neumann Silicon Carbon Ge & III-V mat’ls Strongly correlated mat’ls Quantum state Spin orientation Molecular state Electric charge Strongly correlated electron state Phase state Nanostructured mat’ls Patterns Analog

21. Work in Progress --- Not for Publication 21 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting 2009 ITRS Emerging Research Devices Editorial – Driver Team Meeting Charter and Scope George Bourianoff Mike Garner Jim Hutchby Victor Zhirnov Santa Clara, CA October 13, 2004 Edited December 10, 2006

22. Work in Progress --- Not for Publication 22 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Charter of ERD Chapter On behalf of the 2011 ITRS, develop an Emerging Research Devices chapter to --  Critically assess new approaches to Information Processing technology beyond ultimate CMOS  Identify most promising approach(es) to Information Processing technology to be implemented by 2026 To offer substantive guidance to –  Global research community  Relevant government agencies  Technology managers  Suppliers

23. Work in Progress --- Not for Publication 23 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Scope of ERD Chapter Integrated emerging research memory, logic and new architecture technologies enabled by supporting --  Materials and process technologies  Modeling and simulation  Metrologies Selection of specific technical approaches shall be  Guided by fundamental requirements  Bounded by ERD’s topic selection criteria

24. Work in Progress --- Not for Publication 24 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Scope of ERD Chapter Criteria for Including Technology Entries Devices and Architectures –  Published by 2 or more groups in archival literature and peer reviewed conferences, or  Published extensively by 1 group in archival literature and peer reviewed conferences  Technology Entry (by itself or integrated with CMOS) must address a major electronics market. Materials and Fabrication Technologies –  Materials and processes that address the specific material needs defined by emerging research device technology entries  Supporting disciplines – specify for crosscut TWGs  Metrologies  Modeling & simulation

25. Work in Progress --- Not for Publication 25 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Decisions for 2009 Chapter Fig. 4

26. Work in Progress --- Not for Publication 26 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Decisions for 2009 Chapter Fig. 5

27. Work in Progress --- Not for Publication 27 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Decisions for 2009 Chapter Fig. 6

28. Work in Progress --- Not for Publication 28 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Decisions for 2009 Chapter (Divide into 3 tables to match the three logic tables) Fig. 7

29. Work in Progress --- Not for Publication 29 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting Decisions for 2009 Chapter Fig. 8

30. Work in Progress --- Not for Publication 30 ERD WG 7/10/2011 San Francisco, CA. FxF Meeting “Guiding Principles”  Computational state variable(s) other than solely electron charge. These include spin, phase, multipole orientation, mechanical position, polarity, orbital symmetry, magnetic flux quanta, molecular configuration and other quantum states.  Non-thermal equilibrium systems to reduce the perturbations of the stored information energy by thermal interactions with the environment (e.g., systems that perform all processing functions in a time short compared to the system’s energy relaxation time to improve thermal noise immunity).  Nanoscale thermal management. This might be accomplished by manipulating lattice phonons for constructive energy transport and heat removal.  Novel information transfer mechanisms. These mechanisms would provide the interconnect function between communicating information processing elements, and input/output.  Alternative Architectures. In this case, architecture is the functional arrangement on a single chip of interconnected devices that includes embedded computational components. These architectures should utilize, for special purposes, novel devices other than CMOS to perform unique functions.  Sub-lithographic manufacturing process (e.g., directed self-assembly of complex structures composed of nanoscale building blocks) The approaches should address essential non-regular, hierarchically organized structures, be tied to specific device ideas, and be consistent with high volume manufacturing processes.