1. 1 IN THE NAME GOD Advanced VLSI Class Presentation A 1.1GHz Charge Recovery Logic Insructor : Dr. Fakhrayi Presented by : Mahdiyeh Mehran

2. 2 Adopted From: A 1.1GHz Charge Recovery Logic Visvesh S. Sathe Juang-Ying Chueh Marios C. Papaefthymiou University of Michigan, Ann Arbor, USA

3. 3 Contributions First ever demonstration of fully integrated charge- recovery chip in 0.13  m CMOS at GHz clock rates –Boost Logic : Dynamic charge-recovery circuit family Chain of test gates (1600 gates total) Integrated inductor and clock generator Resonant operation at 850MHz, 1.3V Functional at 1.1GHz, 1.4V Energy recovery rate at resonance = 60%

4. 4 Outline Charge Recovery – Brief overview –Basic Principles Boost Logic structure Boost Logic operation Boost Logic test chip Chip measurement results

5. 5 Brief Overview of Charge Recovery Ref.[1] Gradual transition of power supply (Power-Clock). Supply must enable recovery of charge. Inductor used to resonate power clock. V in VCVC v time I T VCVC + - V in I  CC R

6. 6 Outline Charge Recovery – Brief overview –Basic Principles Boost Logic structure Boost Logic operation Boost Logic test chip Chip measurement results

7. 7 VC = Vdd’ – Vss’ = Vth Vdd’ = (Vdd + Vth)/2 Vss’ = (Vdd - Vth)/2

8. 8 Boost Logic: Hybrid Charge Recovery Ref.[1 ] Two-stage operation : Logic and Boost Logic Stage performs logical evaluation Boost Stage takes output nodes to full rail. out

9. 9 Boost Logic: Hybrid Charge Recovery Ref.[1] Two-stage operation : Logic and Boost Logic Stage performs logical evaluation Boost Stage takes output nodes to full rail.

10. 10 Boost Logic Structure Ref.[1]

11. 11 Outline Charge Recovery – Brief overview –Basic Principles Boost Logic structure Boost Logic operation Boost Logic test chip Chip measurement results

12. 12 Boost Logic Inverter Ref.[1]

13. 13 Boost Logic Operation Ref.[1] Boost Stage deactivated – all 4 devices in cutoff. Clocked transistors turn on, enabling evaluation. Logic stage drives output nodes to conventional rails. 0 1.2 t (s) 0.6 Logic Stage Drives Outputs   out

14. 14 0 1.2 t (s) 0.6 Both Stages Tri-stated Boost Logic Operation Ref.[1] With  = V ss ’ and  = V dd ’ clocked transistors turn off. Boost Stage remains tri-stated from output. Pre-resolved output nodes provided to Boost Stage.  

15. 15 t (s) 0 1.2 0.6 Boost Stage Amplifies Outputs Boost Logic Operation Ref.[1] As  crosses V dd ’ (V ss ’ ), Boost stage turns on. Transistors M2 and M3 turn on. Outputs track power clock.  out 

16. 16 0 1.2 t (s) 0.6 Boost Stage Charge Recovery Boost Logic Operation Ref.[1] As  moves toward V ss (V dd ) –Transistors M2 and M3 turn on. –Charge in load capacitance returns to resonant clock. As V(out) – V(out) ≈ V th, all 4 devices are in cutoff.  out 

17. 17 Cascade Simulation Ref.[1] Logic cascaded with alternate clock phases. V gs ’ < 0 in logic evaluation trees when off. Low V th devices desirable in logic evaluation trees. LogicBoost (V) 0 0.5 1.0 t (s)  out in 0.5n1n0n  i1 i0

18. 18 Outline Charge Recovery – Brief overview –Basic Principles –Previous work Issues with previous charge recovery logic Boost Logic structure Boost Logic operation Boost Logic test chip Chip measurement results

19. 19 Boost Logic Test Chip Ref.[1] Oscillation driven by reference clock. Programmable clock generator –Variable Duty Cycle 0%<D<50% –Variable Switch Width 0<W<450µm

20. 20 Boost Logic gate chains Clock generator switches Programmable Schmitt triggers Boost Logic Test Chip : Die Shot Capacitance per phase = 29pF Inductance = 2.4nH (2 layers, Cu, 0.7µm thick)

21. 21 Outline Charge Recovery – Brief overview –Basic Principles –Previous work Issues with previous charge recovery logic Boost Logic structure Boost Logic operation Boost Logic test chip Chip measurement results

22. 22 Energy/Current Measurements Ref.[1] Energy measured for all possible W, D, V dd and V c At resonance (850MHz): –Energy dissipation in V dd = 26pJ [40% of CV 2 ] –Energy dissipation in V C = 4pJ [V C = 0.45V] Energy Dissipation per Cycle (pJ) Current (mA) Operating Frequency (GHz) Energy Current 25 30 35 40 45 50 25 30 35 40 15 20 0.70.8 0.91.01.1 Resonant Frequency

23. 23 Conclusion First ever charge-recovery test chip to exceed 1GHz clock rate –Boost Logic : Dynamic charge-recovery circuit family Fully-integrated clock generator and inductor in 0.13  m CMOS Functional up to 1.1GHz Resonant frequency = 850MHz Energy recovery rate at resonance = 60%

24. 24 References [1] V. S. Sathe, et al., “A 1.1GHz Charge-Recovery Logic,”ISSCC, pp.388-390, Feb., 2006. [2] V. S. Sathe, et al., “A GHz-Class Charge Recovery Logic,” ISLPED, pp.91-94, Aug., 2005. [3] S. Kim, et al., “True Single-Phase Adiabatic Circuitry,” Transactions on VLSI Systems, pp. 52-63, Feb., 2001. [4] D. Suvakovic, C. Salama, “Two Phase Non-Overlapping Clock Adiabatic Differential Cascode Voltage Switch Logic (ADCVSL),” ISSCC Dig.Tech.Papers, pp. 364-365, Feb., 2000. [5] D. Maksimovic, V. Oklobdzija, B. Nikolic, and K. Current “Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply,”Transactions on VLSI Systems, Aug., 2000.

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