1. Robust Low Power VLSI R obust L ow P ower VLSI Sub-threshold Sense Amplifier (SA) Compensation Using Auto-zeroing Circuitry 01/21/2014 Peter Beshay Department of Electrical Engineering University of Virginia, Charlottesville

2. Robust Low Power VLSI Outline  Motivation  Introduction  DAZ Circuit  16kB SRAM  Chip Measurements  Conclusion 2

3. Robust Low Power VLSI Motivation 3 Source: IdeaConnection.com Source: groups.csail.edu/ Source: Implantable-device.com

4. Robust Low Power VLSI Motivation 4 SRAM are used in implantable devices  Contribute significantly to the total System-on-chip (SOC) power consumption SRAM Power Consumption (1) (1) N. Verma, Phd thesis

5. Robust Low Power VLSI Motivation 5 Minimum Energy occurs in sub-threshold [1] E active = CV DD 2 E total /operation minimized in sub-V T Main Limitations Process Variations effect, Slow Speed VDD (V) Normalized Energy (1) N. Verma, Phd thesis Energy Consumption vs. VDD (1)

6. Robust Low Power VLSI Motivation 6 Work Focus Minimizing the energy of the read operation of sub-threshold SRAMs.  Sense Amplifier are utilized during the read operation of the SRAMs.  The intrinsic offset voltage of the SAs causes increased read energy and degraded performance of the SRAM read operation [2].

7. Robust Low Power VLSI Outline  Introduction  DAZ Circuit  16kB SRAM  Chip Measurements  Conclusion 7

8. Robust Low Power VLSI Sense Amplifier

9. Robust Low Power VLSI 9 SA Offset Voltage

10. Robust Low Power VLSI 10 SA Offset Voltage

11. Robust Low Power VLSI 11...... SAE Row Decoder 6T Bitcell............ … 6T SRAM Read Operation

12. Robust Low Power VLSI 12...... SAE Row Decoder 6T Bitcell............ … 6T SRAM Read Operation

13. Robust Low Power VLSI 13...... SAE Row Decoder 6T Bitcell............ … 6T SRAM Read Operation

14. Robust Low Power VLSI 14...... SAE Row Decoder 6T Bitcell............ … 6T SRAM Read Operation

15. Robust Low Power VLSI 15...... SAE Row Decoder 6T Bitcell............ … 6T SRAM Read Operation

16. Robust Low Power VLSI 16...... SAE Row Decoder 6T Bitcell............ … WL 6T SRAM Read Operation

17. Robust Low Power VLSI 17...... SAE Row Decoder 6T Bitcell............ … 01 WL 6T SRAM Read Operation

18. Robust Low Power VLSI 18...... SAE Row Decoder 6T Bitcell............ … 01 WL 6T SRAM Read Operation

19. Robust Low Power VLSI 19...... SAE Row Decoder 6T Bitcell............ … 01 WL ∆V 6T SRAM Read Operation

20. Robust Low Power VLSI 20...... SAE Row Decoder 6T Bitcell............ … 01 WL SAE ∆V 6T SRAM Read Operation

21. Robust Low Power VLSI 21...... SAE Row Decoder 6T Bitcell............ … 01 WL SAE ∆V 6T SRAM Read Operation

22. Robust Low Power VLSI 22...... SAE Row Decoder 6T Bitcell............ … 01 WL SAE Pre-charge ∆V 6T SRAM Read Operation

23. Robust Low Power VLSI 23...... SAE Row Decoder 6T Bitcell............ … 01 WL SAE Pre-charge ∆V 6T SRAM Read Operation

24. Robust Low Power VLSI 24...... SAE Row Decoder 6T Bitcell............ … 01 WL SAE Pre-charge ∆V 6T SRAM Read Operation

25. Robust Low Power VLSI PMOS-input Latch SA BL OUT M5 M6 M1 M2 M3 M4 Cross coupled inverter to latch the output Sense the input voltage Enable the SA Precharge the output to VDD 25

26. Robust Low Power VLSI BL=0.45V OUT M5 M6 M1 M2 M3 M4 EN 26 PMOS-input Latch SA

27. Robust Low Power VLSI BL=0.45V OUT M5 M6 M1 M2 M3 M4 EN 27 PMOS-input Latch SA

28. Robust Low Power VLSI Offset Voltage BL=0.5 OUT M5 M6 M1 M2 M3 M4 28

29. Robust Low Power VLSI 29 Digital Auto-zeroing (DAZ) We propose a digital auto-zeroing (DAZ) scheme inspired by analog amplifier offset correction. The main advantages of the approach are Near-zero offset after cancellation. Suitable for sub-threshold operation due to the repeated offset compensation phase. Several attempts have been made before to tackle the problem including: Redundancy [3] Transistor upsizing [4] Digitally controlled compensation [5]

30. Robust Low Power VLSI Outline  Introduction  DAZ Circuit  16kB SRAM  Chip Measurements  Conclusion 30

31. Robust Low Power VLSI Auto-zeroing in analog amplifiers Amplification is done in two phases Φ1: Sample the offset on a capacitor Φ2: Subtract the offset from the input signal (2) K Kang et al, “Dynamic Offset Cancellation Technique” cse.psu.edu/~chip/course/analog/insoo/S04AmpOffset.ppt‎ Dynamic Offset Cancellation (2)

32. Robust Low Power VLSI DAZ Scheme Phase1 (ENR1) A zero differential input is applied to the sense amp. Phase2 (ENO) The SA resolves based on its intrinsic offset.

33. Robust Low Power VLSI DAZ Scheme Phase3 (ENR2) The differential input is applied to the sense amp. Phase4 (ENI) The SA resolves based on the differential input.

34. Robust Low Power VLSI DAZ Circuit ENR1 OUT M5 M6 M1 M2 M3 M4 ENR1 ENR2 ENI BL ENR2 ENI MC2 MC1 DAZ circuit applied to a latch-based sense amp with PMOS inputs DAZ circuit uses a split-phase clock and charge pump (CP) feedback circuit for repetitive compensation. Charge Pump

35. Robust Low Power VLSI DAZ Circuit ENR1 OUT M5 M6 M1 M2 M3 M4 ENR1 ENR2 ENI BL ENR2 ENI MC2 MC1 Charge Pump Transistors MC1 and MC2 control the drive strength of the right side of the SA. The CP controls the drive current in both MC1 and MC2 to equalize the strength of the SA right and left sides.

36. Robust Low Power VLSI DAZ Circuit ENR1 OUT M5 M6 M1 M2 M3 M4 ENR1 ENR2 ENI BL ENR2 ENI MC2 MC1 M11 ENO ENR2 M9 M10 M12 M13 Cp Charge Pump

37. Robust Low Power VLSI Phase 1 ENR1 OUT M5 M6 M1 M2 M3 M4 ENR1 ENR2 ENI BL ENR2 ENI MC2 MC1 M11 ENO ENR2 M12 M13 Cp M9 M10 ER1: A zero differential input is applied to the sense amp. Charge Pump

38. Robust Low Power VLSI Phase 2 ENR1 OUT M5 M6 M1 M2 M3 M4 ENR1 ENR2 ENI BL ENR2 ENI MC2 MC1 M11 ENO ENR2 M12 M13 Cp M9 M10 ENO: The SA resolves based on its intrinsic offset. Charge Pump

39. Robust Low Power VLSI Phase 3 ENR1 OUT M5 M6 M1 M2 M3 M4 ENR1 ENR2 ENI BL ENR2 ENI MC2 MC1 M11 ENO ENR2 M12 M13 Cp M9 M10 ER2: The differential input is applied to the sense amp. Charge Pump ∆v

40. Robust Low Power VLSI Phase 4 ENR1 OUT M5 M6 M1 M2 M3 M4 ENR1 ENR2 ENI BL ENR2 ENI MC2 MC1 M11 ENO ENR2 M12 M13 Cp M9 M10 ENI: The SA resolves based on the differential input. Charge Pump

41. Robust Low Power VLSI 41 Precision The precision of the scheme depends on the accuracy of setting the voltage on the output capacitor (Cp). Settling Time = 60us

42. Robust Low Power VLSI 42 Offset Tuning Accuracy (offset voltage) vs. settling time trade-off through Cp tuning. Cp=0.74pF Cp=0.43pF Cp=0.24pF Cp=0.14pF Cp=0.13pF

43. Robust Low Power VLSI Outline  Introduction  DAZ Circuit  16kB SRAM  Chip Measurements  Conclusion 43

44. Robust Low Power VLSI 44 16kB SRAM Test-case A 20mV DAZ SA is used in a 16kB SRAM with 1bank, 512 rows and 256 columns using commercial 45nm technology node [6]. 10% reduction of the read energy 24% reduction of the read delay 45nm technology test chip. One regular SA array for benchmarking DAZ SA array with Cp=32fF. DAZ circuit limits the absolute value of the maximum offset to 50 mV and provided 80% improvement in σ [6]. Chip Measurements

45. Robust Low Power VLSI 45 Limitation Area overhead (major concern in SRAM designs) 2.5X for 50mV offset compensation Can be significant for small offsets Energy overhead of the continuous calibration (split phases, charge pump) 3.5X the energy of a regular SA Sensitivity to split phase frequency.

46. Robust Low Power VLSI Outline  Introduction  DAZ Circuit  16kB SRAM  Chip Measurements  Conclusion 46

47. Robust Low Power VLSI 47 Conclusion We proposed a circuit that is capable of improving sense-amp offset to near zero, which is valuable for sub-threshold operation due to the repeated calibration phase. Applying the scheme on a 16 kB SRAM in 45nm technology node showed a reduction in the total energy and delay of 10% and 24% respectively. Measurements from a test chip fabricated in 45 nm technology showed the circuit’s‎ ability ‎to ‎limit‎ the absolute maximum value of the offset voltage to 50 mV using a 32fF output capacitance.

48. Robust Low Power VLSI 48 References 1.B. H. Calhoun et al. "Sub-threshold circuit design with shrinking CMOS devices." ISCAS 2009. 2.J. Ryan et al. “Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation” ISQED 2008. 3.N. Verma et al. “A 256 kb 65 nm 8T Sub-threshold SRAM Employing Sense-Amplifier Redundancy” ISSCC 2008. 4.L. Pileggi et al. “Mismatch Analysis & Statistical Design” CICC 2008. 5.M. Bhargava et al. “Low-Overhead, Digital Offset Compensated, SRAM Sense Amplifiers” CICC 2009. 6.P. Beshay et al. "A Digital Auto-Zeroing Circuit to Reduce Offset in Sub- Threshold Sense Amplifiers." JLPEA 2013

49. Robust Low Power VLSI 49 Questions