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CASES 2002 Intl Conference on Compilers, Architectures and Synthesis for Embedded Systems Embedded Architectures: Configurable, Re-configurable, or what?

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Presentation on theme: "CASES 2002 Intl Conference on Compilers, Architectures and Synthesis for Embedded Systems Embedded Architectures: Configurable, Re-configurable, or what?"— Presentation transcript:

1 CASES 2002 Intl Conference on Compilers, Architectures and Synthesis for Embedded Systems Embedded Architectures: Configurable, Re-configurable, or what? (position statements) Reiner Hartenstein University of Kaiserslautern viewgraph downloading, for a link see: Grenoble, France October Pierre Paulin, STMicro (moderator); Henk Corporaal, IMEC; Reiner Hartenstein, University of Kaiserslautern; Oz Levia, Improv Systems; Marco Pavesi, Italtel; Chris Rowen, Tensilica. Thursday, Oct 10, session 5, p.m. Re-configurable !

2 © 2002, University of Kaiserslautern 2 Re-configurable Hardware ?? this Hardware is not hard ! We need a concise terminology: a consensus is on the way its Morphware Terminology has been highly confusing

3 © 2002, University of Kaiserslautern 3 Terminology: DPU versus CPU... DPU: data path unit DPA: DPU array GA: gate array rDPU: reconfigurable DPU rDPA: reconfigurable DPA rGA: reconfigurable GA DPU is no CPU: there is nothing central - like in a DPA DPU instruction sequencer CPU DPA (r)(r) (r)(r)

4 © 2002, University of Kaiserslautern 4 Digital System Platforms clearly distinguished platform program source running on it machine paradigm hardware (not programmable) none morphware fine grainrGA (FPGA) configware coarse grain rDPU, rDPA reconfigurable data stream processor flowware & configware anti machine data stream processor (hardwired)flowware instruction stream processorsoftware von Neumann machine

5 © 2002, University of Kaiserslautern 5 flowware defines.... time port # time DPA x x x x x x x x x | || xx x x x x xx x -- - input data streams xx x x x x xx x x x x x x x x x x | | | | | | | | | | | | | | output data streams time port # time port #... which data item at which time at which port flowware manipulates the data counter (s) software manipulates the program counter

6 © 2002, University of Kaiserslautern 6 Configware / Flowware Compilation r. Data Path Array rDPA intermediate high level source program wrapper address generator configware mapper flowware scheduler MMMM MMMM M M M M M M M M data streams data sequencer

7 © 2002, University of Kaiserslautern 7 most important contributor to nano SoC we need rDPAs for: cellular wireless multimedia other applications relative merits: performance flexibility time to market product longevity key functionalities: to cope with compute requirements unstable standards multiple standards

8 © 2002, University of Kaiserslautern Processor Performance microprocessor / DSP Normalized processor speed Memory (Moores Law) Transistors/chip 2G 3G 4G 1G wireless Algorithmic Complexity (Shannons Law) Normalized processor speed

9 © 2002, University of Kaiserslautern 9 Performance vs. Flexibility flexibility throughput ,07 MOPS / mW µ feature size DeMan [T. Claasen et al.: ISSCC 1999] hard- wired hardwired von Neumann instruction set processors standard microprocessor DSP FPGA Reconfigurable logic rDPAs go far beyond bridging the gap rDPA *) R. Hartenstein: ISIS 1997 rDPAs (reconfigurable computing)*

10 © 2002, University of Kaiserslautern 10 cSoC for wireless communication et al. Layout for UMC 0.13 mm CMOS Xtreme processing unit (XPU) from PACT incremental dynamic reconfiguration rDPA

11 © 2002, University of Kaiserslautern 11 Time to Market A Fundamental Paradigm Shift in Silicon Application Revenue / month Time / months ASIC Product 30 Update 1 Product Update 2 reconfigurable Product with download [Tom Kean]

12 © 2002, University of Kaiserslautern 12 © 2001, University of Kaiserslautern >>> END END

13 © 2002, University of Kaiserslautern 13 © 2001, University of Kaiserslautern >>> Appendix Appendix for discussion

14 © 2002, University of Kaiserslautern 14 stolen from Bob Colwell Why a dichotomy of machine paradigms? CPU caches,... vN bottleneck data stream machine: bad message: caches do not help good message: no vN bottleneck caches not needed vN: unbalanced

15 © 2002, University of Kaiserslautern 15 Soap Chip* Platform Template microProg peripherals RISC, VLIW Config. MCU ASIP S/W RISC, VLIW Gen. Purp. RISC, VLIW S/W Scalable SoC interconnect ASIC Mem Processor Standard I/O blocks ROM, Flash eSRAM eDRAM Config. DSP Config. DSP S/W Configware Software S/W C/W RC rDPA FPGA eFPGA Standard H/W IP C/W © 2002, important: coarse grain morphware *) System on a programmable Chip

16 © 2002, University of Kaiserslautern 16 Anti machine data stream machine flowware Programming sources von Neumann instruction stream machine reconfigurable or hardwired hardwired only

17 © 2002, University of Kaiserslautern 17 Machine paradigms Software von Neumann data-stream machine embedded memory architecture* Configware Flowware instruction stream machine

18 © 2002, University of Kaiserslautern 18 Cost new business model needed design cost year product life cycle the key enabler: morphware

19 © 2002, University of Kaiserslautern 19 Glossary DPUdata path unit rDPUreconfigurable DPU DPAdata path array (DPU array) rDPAreconfigurable DPA ISPinstruction set processor AManti machine AMPdata stream processor* rAMPreconfigurable AMP *) no dataflow machine platform category source running on platform machine paradigm hardware (not programmable) none ISP**software von Neumann morphwareconfigware FPGA: none data stream processor (AMP*) flowware anti machine reconfigurable AMP (rAMP) flowware & configware digital system platforms: morphware usegranularity (path width) (re)configurable blocks reconfigurable logicfine grain (FPGA) (~1 bit)CLBs reconfigurable computing coarse grain (e.g. 32 bits)rDPUs (e.g. ALU-like) multi granular: by slice bundlingrDPU slices (e.g. 4 bits) categories of morphware: approaching consensus **) instruction set processor *) data stream processor


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