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VHDL Design of Multifunctional RISC Processor on FPGA A.Girish Pawan Kumar V.Raghavendran S.Sudarsan V.Swaminathan.

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Presentation on theme: "VHDL Design of Multifunctional RISC Processor on FPGA A.Girish Pawan Kumar V.Raghavendran S.Sudarsan V.Swaminathan."— Presentation transcript:

1 VHDL Design of Multifunctional RISC Processor on FPGA A.Girish Pawan Kumar V.Raghavendran S.Sudarsan V.Swaminathan

2 VLSI Basics VLSI-Very large scale integrated circuit. Electronic system with integrated dedicated components. Semi custom and full custom. Design styles-ASIC,PLD,CPLD,FPGA,system on chip. FPGA-RAM based devices,these devices loose their configuration when power is switched off. FPGA uses hex file for design. FPGA programming-Verilog and VHDL.

3 VHDL basics VHDL-Very high speed IC Hardware Description Language. Modeling of digital system. Concurrent and sequential statements. Man and machine readable specification. Simulatable source code. Modeling Behavioral,structural,data flow. Features Strongly typed-describes from abstract to concrete level. Case insensitive. Top- down and down-top methods. Flexible design methods.

4 What is RISC? Computer arithmetic-logic unit. Fastest instruction execution. Instructions are of same size and execute within a single cycle. Efficient way of completing a operation. Reduces hardware space complexity. Properties Smaller number of instruction commands. Single word standard length. Large general purpose CPU registers. Less costly to design, test and manufacture. Fixed length and easy decoder format.

5 CISC Vs RISC CISC Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Small code sizes, high cycles per second Transistors used for storing complex instructions RISC Emphasis on software Single-clock, reduced instruction only Register to register: "LOAD" and "STORE" are independent instructions Low cycles per second, large code sizes Spends more transistors on memory registers

6 Features An 8 bit processor. Designed for achieving one clock per instruction. Memory facilitates the control unit with the instructions which in turn generates appropriate signals for rest of the processor. Provides four to ten times better performances than existing micro controllers. Data path


8 INSTRUCTION MEMORY INSTRUCTION DECODER ROM 5-bit Address 16-bit Data Multiple output logic circuit Control Signals Instruction and address

9 REGISTER ALU BLOCK group of flip-flops to store 1-bit information. both storing and retrieving data. arithmetic and logic functions on 8-bit data. addition, subtraction, excess 3, increment, decrement compare,logic gates, Shifting operations, complement.

10 Stepper Motor Control Electromechanical Device Stator Rotor Field coils

11 Simulation MODELSIM software Mixed language simulator Design up and running is quick Test benches-regression test Low cost,consumes less time and good performance. Signals in design-waveform generation.


13 Synthesis Converting higher level of abstraction to lower level of abstraction Higher level-HDL language Lower level-equivalent gate level implementation of HDL language Xilinx synthesis technology-project navigator Project Navigator-design source files,run processes,view output. It integrates the tools and process is designed easily.



16 Kit Specifications INPUT: 230V,50Hz. OUTPUT: +5V DC. LCD: 16*2 display. LED:16 digital I/O indication. DIP switches:inputs and outputs. 4 x 3 Keypad CPLD,micro controller,clock provider. ADC,DAC. FPGA - XC 2S 150,plastic quad,208 pins,15MHZ. MICRO CONTROLLER - ATMEL 89C519,18.432MHZ. 40 I/Os of the device are available for external use.

17 Spartan II Kit

18 Configuration SANDS FPGA DEVELOPMENT PLATFORM Software -Configures FPGA device and checks for functionality -Transferring the hex file from the system to the kit.

19 Applications Engineering and Graphic work station. Parallel processing systems. Ideal for Embedded applications (mobile phones, digital cameras, etc). Apple iMAC RISC inside the system

20 Conclusion RISC is an evolution in computer architecture. Emphasizes on speed and cost-effectiveness over the ease of assembly-language programming and conservation of memory. RISC-based designs will continue to grow in speed and ability, more rapidly than CISC design. FUTURE TRENDS The features of RISC processor can be extended by including Program Counter, Generic Statement, Load and Store instructions. This facilitate running the program continuously, increasing the number of bits.


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