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FPGA Field Programmable Gate Array With an overview of different Reconfigurable Technologies Presented by: Ramtin Raji Kermani (http://www.cse.shirazu.ac.ir/~ramtinraji)

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Presentation on theme: "FPGA Field Programmable Gate Array With an overview of different Reconfigurable Technologies Presented by: Ramtin Raji Kermani (http://www.cse.shirazu.ac.ir/~ramtinraji)"— Presentation transcript:

1 FPGA Field Programmable Gate Array With an overview of different Reconfigurable Technologies Presented by: Ramtin Raji Kermani (http://www.cse.shirazu.ac.ir/~ramtinraji) Senior student of Computer Engineering Shiraz University Spring 2006

2 Covered subjects What is Reconfigurable Computing? Application Specific Integrated Circuits (ASICs) Programmable Logic Devices (PLDs) Programmable Logic Arrays (PLAs) Field Programmable Gate Array : FPGA Why FPGA? FPGA Architecture FPGA Implmentation FPGA design Process Hardware Description Languages : HDLs

3 What is Reconfigurable Computing? Concept from 1960s, But still a new field of research. The ability to change the Processing unit at Run-Time. Computer processing with highly flexible computing fabrics. The ability to changes the data path, in addition to the control flow. Run-Time and On-board reconfiguration A Computer consisting: A Standard processor An array of reconfigurable hardware Initial Ideas … Software Flexibility Hardware Speed

4 Reconfigurable Logic Characteristics: 1. Granularity: size of the smallest functional unit (CLB) Low granularity (Fine-Grained) : like FPGAs Greater Flexibility Increased power, delay, area due to greated Qtty. of routing Bit level manipulation High granularity (Coarse-grained) : like rDPAs Consists of big elements Optimized for standard data path applications Drawback: loosing some of its utilisation for smaller computations Word-with data paths A larger block instead of smaller connected units What is Reconfigurable Computing?

5 Reconfigurable Logic Characteristics: 2. Rate of Configuration: Reconfiguration can happen at deployment time Between execution or During execution (at Run-Time) Bit streams is used t reprogram the device at Deployment time Fine grained systems require more config. Time Partial Reconfiguration: A part is being reconfgured while the other is performing What is Reconfigurable Computing? 3. Routing / Interconnects: Flwxibility of a Reconfigurable Device come from its routing interconnects Island Style Layout: Blocks in Vertical and Horizental routing (in FPGAs)

6 What is Reconfigurable Computing? Island Style layout

7 Application Specific Integrated Circuits : ASICs Used to design a system on a chip To do a VERY specific job, no reconfiguration Interconnect of standard cells Highly automated design flow ASICs design flow: 1.RTL description 2.Functional simulation 3.Synthesis 4.Design verification 5.Layout

8 Processors Vs. ASICs Processors: Take longer to compute Slow Flexible Need instructions to determine what to do on each cycle ASICS: Take shorter time to compute Fast Not Flexible No instruction Same calculation every cycle

9 Processors Vs. ASICs Actual computation Processor ASIC

10 Processors Vs. ASICs TemporalSpatial Single Processor ASIC Slow Flexible Fast Inflexible Reconfigurable Computing ?

11 Programmable array logic: PAL A programmable Logic Device Used to implement combinational logic circuits First introduced by Monolithic Memories Inc. (MMI) in 1978 Priviously FPLA by Signetics (1975)

12 Field programmable Gate Arrays dimensional array of logic blocks and flip-flops with a electrically programmable interconnections FPGA provides its user a way to configure: The intersection between the logic blocks The function of each logic block. FPGA Logic Blocks can be configured to offer functions: As simple as a transistor As Complex as a CPU

13 Simplified FPGA Architecture

14 Block Interconnections (Switch Box)

15 FPGA Logic Blocks FPGAs has four different logic block structures: 1.Crosspoint FPGA 2.Plessey FPGA 3.Actel Logic Block 4.Xilinx Logic block

16 Crosspoint FPGA Crosspoint FPGA: consist of two types of logic blocks. One is transistor pair tiles in which transistor pairs run in parallel lines as shown in figure below:

17 Plessey FPGA Plessey FPGA: basic building block here is 2-input NAND gate which is connected to each other to implement desired function.

18 Actel Logic Block Actel Logic Block: If inputs of a multiplexer are connected to a constant or to a signal, it can be used to implement different logic functions.

19 Xilinx Logic block: Xilinx Logic block: Look up table is used to implement any number of different functionality.

20 SRAM programming technology Static RAM cells are used to control pass gates or multiplexers

21 Floating Gate Programming The programmable switch is a transistor that permanently be disabled

22 FPGA Design Flow The FPGA design process of xillinx products are as follows: (the other products have similar process) For more info : toolbox.xilinx.com/docsan/xilinx7/help/iseguide/html/ise_fpga_design_flow_overview.htm

23 Hardware Description Languages: HDLs For programming FPGAs, we need a special kind of programming language to describe hardware functions. Three Major HDLs: 1.VHDL (VHSIC Hardware Description Language) 2.VeriLog 3.JHDL (Java implementation as HDL)

24 References As Always: My dear GoOgLe : !!! Introduction to Reconfigurable Computing, Hayden So Digital Logic Circuit Analysis & Design, V.Nelson XILINX documentations ACTEL documentation

25 The End … Questions ? Comments ?


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