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Von Neumann Architectures and the PDP-8. A computer is an electronic (?) device operating under control of instructions stored in its own memory unit.

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Presentation on theme: "Von Neumann Architectures and the PDP-8. A computer is an electronic (?) device operating under control of instructions stored in its own memory unit."— Presentation transcript:

1 Von Neumann Architectures and the PDP-8

2 A computer is an electronic (?) device operating under control of instructions stored in its own memory unit (stored program concept) that accepts data (input) processes data arithmetically and logically displays information (output) from the processing and/or stores the results for future use.

3 The von Neumann Model The von Neumann model consists of five major components: (1) input unit; (2) output unit; (3) arithmetic logic unit; (4) memory unit; (5) control unit. Source: Computer Architecture and Organization by M. Murdocca & V. Heuring Fig 1-13 page 10

4 The System Bus Model A refinement of the von Neumann model, the system bus model has a CPU (ALU and control), memory, and an input/output unit. Communication among components is handled by a shared pathway called the system bus, which is made up of the data bus, the address bus, and the control bus. There is also a power bus, and some architectures may also have a separate I/O bus. Source: Computer Architecture and Organization by M. Murdocca & V. Heuring Fig 1-14 page 10

5 Seven Properties of Von-Neumann Architectures G. Blaauw and F. Brooks on page 589 of their book Computer Architecture - Concepts and Evolution list seven "salient features" of von-Neumann architectures as proposed in the 1946 paper "Preliminary discussion of the logical design of an electronic computing device" by A. Burks, H. Goldstine, and J. von Neumann.Preliminary discussion of the logical design of an electronic computing device 1.Single stream of instructions sequenced by instruction counter 2.Instructions stored with data in addressable memory 3.Instructions encoded as numbers - modifiable by arithmetic operations 4.Radix 2 (binary) 5.Word length long enough for scientific computation 6.Single Address - single operation instructions 7.Single Accumulator with MQ Register

6 Stored Program Concept: 1.Instructions stored with data in addressable memory 2.Instructions encoded as numbers - modifiable by arithmetic operations Addressable Memory: 1.Memory accessed by its numeric address (location in memory) 2.Distinction between address of memory and contents at that address

7 Studying Computer Architecture: We look at three things Memory: How is memory structured/organized? What is the size in bits of the smallest addressable cell in memory? Is memory word addressable or byte addressable. What is the memory address space (size of memory)? How are physical addresses obtained from logical addresses? Processor/CPU: Registers: size and number, general purpose vs. special purpose. What ALU operations are supported? Instruction Set: What is the instructions mix? What is the instruction format and how many are there? What addressing modes are supported? The instruction set defines the architecture.

8 The PDP-8 Introduced in 1965 by Digital Equipment Corp. (DEC) – priced at $18K (cheap!) Transistor technology (2 nd generation technology) Considered/marketed as a mini-computer 12–bit word-addressable; 4096 words of memory; 8 op-codes 16 bit byte-addressable very successful PDP-11 was the (market) successor

9 The PDP-8 Emulator Program

10 PDP-8 Bits Words and Integer Representation 12 bit words – bit numbering left to right msb-> <-lsb normally represented in octal binaryOctalbinaryoctal

11 Organization of PDP-8 Memory (2 12 ) words 2.12 bit physical addresses 3.memory organized into 32 pages of 128 words 4.page/offset logical addressing scheme bits 0 – 4: page; bits 5 – 11: offset 5.zero page /current page addressing

12 PDP-8 Registers 1.12 bit accumulator 2.1 bit link register for carry out | | | | | | | | | | | | | | | Link Accumulator 1.12 bit PC (program counter) holds address of next instruction 2.3 bit IR (instruction register) holds current op-code 3.12 MQ register – needed for multiplication/division 4.12 bit Central Processor Memory Register (CPMA) holds address to access memory 5.12 bit Memory Buffer Register (MB) – hold contents of memory access

13 Input/Output 1.Its complicated Problem of data format conversion How do you synchronize a fast CPU with a slow I/O device? 2.Restricted to reading and writing single ASCII characters 3.Uses busy waiting loop 4.Keyboard and printer (TTY device) have data buffers and 1-bit ready flag for synchronization

14 PDP-8 Instructions Memory Reference Instructions | opcode |IA |MP | offset address | Opcode 6 (I/O) Instructions | 1 | 1 | 0 | device number | function | Opcode 7 Microinstructions (3 sub-groups) | 1 | 1 | 1 ||0 |CLA|CLL|CMA|CML|RAR|RAL|0/1|IAC| Where individual bits control micro-functions

15 Addressing Modes MRI instructions Effective Address (Eaddr) = Address of Operand 1.Zero Page Addressing EAddr = offset 2.Current Page Addressing EAddr = Instr Address [0…4] + offset 3.Indirect Addressing 4.Auto-Indexing

16 PDP-8

17 Seven Properties of Von-Neumann Architectures Recall the seven Blaauw and Brooks "salient features" of von- Neumann architectures 1.Single stream of instructions sequenced by instruction counter 2.Instructions stored with data in addressable memory 3.Instructions encoded as numbers - modifiable by arithmetic operations 4.Radix 2 (binary) 5.Word length long enough for scientific computation 6.Single Address - single operation instructions 7.Single Accumulator with MQ Register

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19 Machine language coding the PDP-8

20 12-bit Twos Complement Binary Representation | s | b | b | b | b | b | b | b | b | b | b | b | where s has weight = = = = = = = = -4

21 Nine PDP-8 Machine Codes 1Twos Complement Add (Load Accumulator) 2Increment and Skip (Next Instruction) if Zero 3Deposit and Clear Accumulator 5Jump 7041 Negate Accumulator 7300 Clear Accumulator and Link 7402 Halt 7500 Skip Next Instruction if Accumulator is Negative 7510 Skip Next Instruction if Accumulator is Positive


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