1. FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved Basic FPGA Configuration Part 1

2. Welcome If you are new to FPGA design, this module will help you understand the configuration process These configuration techniques apply to all of Xilinx’s newest FPGAs, including Spartan-6 and Virtex-6

3. Describe the purpose of each of the FPGA configuration pins Explain the differences between the available configuration schemes Choose an appropriate FPGA configuration scheme for your application After completing this module, you will able to:

4. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 4 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 4 © 2009 Xilinx, Inc. All Rights Reserved Introduction What is configuration? Process for loading configuration data into the FPGA Configuration Data Source Configuration Data Source FPGA Control Logic (Optional) Control Logic (Optional)

5. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2009 Xilinx, Inc. All Rights Reserved Introduction When does configuration happen? On power up On demand Why do FPGAs need to be configured? FPGA configuration memory is volatile Configuration data is stored in a PROM or other external data source What do you need to know about FPGA configuration? What happens during configuration How to set up various configuration modes and daisy chains

6. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2009 Xilinx, Inc. All Rights Reserved FPGA FPGA Configuration Methods Xilinx Cables : JTAG Slave Serial Slave SelectMAP Microprocessor : JTAG Slave Serial Slave SelectMAP Xilinx PROMs : Slave/Master Serial Slave/Master SelectMAP Commodity Flash : Slave SelectMAP SPI* BPI* *SPI and BPI support is available in Spartan™-6, Virtex™-6, and some older FPGA families

7. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2009 Xilinx, Inc. All Rights Reserved FPGA Configuration Process To understand the configuration process, you need to know about… Configuration pins – define the configuration mode Some configuration pins are inputs (active switches), while others are outputs (status indicators) Configuration modes – is the current configuration scheme FPGA designs can support multiple configuration modes – This will require the user to build additional control logic to drive the configuration pins – Be careful, many debugging issues involve multiple configuration modes being used at one time

8. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2009 Xilinx, Inc. All Rights Reserved Configuration Pins Specific pins on the FPGA are used during configuration Some pins act differently depending on the configuration mode Example: CCLK is an output in some modes and an input in others Some pins are only used in specific configuration modes

9. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2009 Xilinx, Inc. All Rights Reserved Configuration Pins Mode pins (3) Input pin(s) that select which configuration mode is being used PROGRAM_B Input that initiates configuration Active Low CCLK (configuration clock) Input or output (depending on configuration mode) Frequency up to 100 MHz (dependent on the FPGA, see configuration user guide) INIT_B Open-drain bi-directional pin Error and power stabilization flag Active Low DONE Open-drain bi-directional pin Indicates completion of configuration process

10. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2009 Xilinx, Inc. All Rights Reserved Configuration Pins DIN Serial input for configuration data DOUT Output to the next device in a daisy chain Used in daisy chains only …other pins are used for specific configuration modes Note that some configuration pins are dual purpose They become user I/O after configuration is complete This is often prohibited by the user

11. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2009 Xilinx, Inc. All Rights Reserved Many Configuration Modes Serial (one data line) JTAG Primarily for debugging and prototyping, recommended for all applications, external control logic provided by download cable and JTAG chain Master Serial Control logic is a part of the FPGA, uses serial Flash (such as Platform Flash PROM) Slave Serial External control logic is necessary, built by user SPI (Serial Peripheral Interface) Control logic in FPGA, uses an industry-standard SPI Flash PROM, usually used in embedded applications Parallel (8-bit or 16-bit data lines) Master SelectMAP Control logic is a part of the FPGA, uses parallel Flash (such as Platform Flash) Slave SelectMAP External control logic necessary, built by user BPI (Byte-Wide Peripheral Interface) Control logic is a part of the FPGA, uses an industry-standard NOR Flash, usually used in embedded applications

12. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2009 Xilinx, Inc. All Rights Reserved JTAG Configuration Mode TCK is driven by your Xilinx programming cable The bitstream is stored on your computer and is downloaded via the ISE™ software iMPACT utility and a Xilinx programming cable Primarily used for debugging Control signals are in parallel Unique programs are shifted into the appropriate device FPGA ISE (iMPACT) + Cable ISE (iMPACT) + Cable TDI FPGA TCK TMS TDO

13. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2009 Xilinx, Inc. All Rights Reserved Master Serial Configuration Mode FPGA provides all control logic All mode pins are tied Low Slave serial mode requires external control logic Master Serial mode FPGA drives configuration clock (CCLK) as an output Data is loaded 1 bit per CCLK Used when data is stored in a serial PROM (usually a Xilinx Platform Flash PROM) Slowest configuration mode, but the easiest to debug Xilinx Platform Flash PROM Xilinx Platform Flash PROM FPGA CCLK Data

14. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2009 Xilinx, Inc. All Rights Reserved Slave Serial Configuration Mode External control logic required to generate CCLK Microprocessor or microcontroller Xilinx serial download cable Another FPGA could be used to build the control logic Daisy chains are often used in this mode Data is loaded 1 bit per CCLK All mode pins are tied High Serial Data Serial Data FPGA Control Logic Control Logic Data CCLK

15. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2009 Xilinx, Inc. All Rights Reserved Master SelectMAP Mode FPGA provides all control logic Sometimes called Master Parallel mode FPGA drives address bus Data is loaded 1 byte per address Data internally serialized FPGA generates 8 CCLKs per byte Usually targets Xilinx Platform Flash XL or another vendors Platform Flash PROM The Xilinx Platform Flash XL also works in BPI mode and is a popular memory resource for Virtex-5 and Virtex-6 This enable faster configuration times Byte-Wide Data Source Byte-Wide Data Source FPGA CCLK Data

16. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2009 Xilinx, Inc. All Rights Reserved Slave SelectMAP Mode External control logic required (microprocessor or microcontroller, for example) Ready/Busy handshaking Data presented 1 byte at a time Virtex-5 and Virtex-6 support x8, x16, and x32 Spartan-6 supports x8 and x16 Asynchronous Peripheral Control logic provides a Write strobe Triggers FPGA to generate 8 CCLK pulses Can target Xilinx Synchronous Peripheral CCLK provided by control logic (8 pulses per data byte) Platform Flash XL This would not require external control logic Byte-Wide Data Byte-Wide Data FPGA Control Logic Control Logic Data Ready/Busy Control Signals

17. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2009 Xilinx, Inc. All Rights Reserved Serial Peripheral Interface (SPI) Mode FPGA configures itself from an attached industry-standard SPI serial Flash PROM FPGA issues a command to Flash and it responds with the data Can be used in multi-boot applications where multiple bitstreams can be loaded by the FPGA Data is loaded 1 bit per CCLK (slow) There are no standards for the commands Commands are vendor specific Vendor Select (VS) pins tell the FPGA which commands to issue Spartan™-6 supports x2 and x4 modes See Data Sheet or Configuration User Guide for list of supported vendors Excellent choice for embedded applications SPI Flash PROM SPI Flash PROM FPGA Data Command CCLK

18. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2009 Xilinx, Inc. All Rights Reserved Byte-Wide Peripheral Interface (BPI) Mode FPGA issues an address to a BPI Flash, which responds with the data Uses standard parallel NOR Flash interface No clock is needed because the FPGA contains the control logic Usually used in embedded applications Flash is easily used as addressable memory with address and data buses Supported for Virtex™-5, Virtex-6, Spartan™-3E, and Spartan-6 FPGAs Xilinx Platform Flash XL is a 128 Mb parallel NOR and works in BPI and SelectMAP modes Spartan-6 BPI mode is shared with SelectMAP mode BPI NOR Flash BPI NOR Flash FPGA Data Addr[26:0]

19. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2009 Xilinx, Inc. All Rights Reserved Summary Field programmable gate arrays are usually configured on power up from an external data source SPI and BPI are the simplest configuration modes and take the least effort to debug, because the control logic is already built Slave configuration modes require you to build the external control circuitry JTAG access enables much easier testing and debugging of your prototype and while your system is in production

20. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2009 Xilinx, Inc. All Rights Reserved Where Can I Learn More? Configuration User Guides (from the ISE tools) Help  Xilinx on the Web  (select a device family)  FPGA User Guides Virtex-6 FPGA Configuration User Guide, UG360 Spartan-6 FPGA Configuration User Guide, UG380 Virtex-5 FPGA Configuration User Guide, UG191 (older Spartan families), UG332 Platform Flash XL Configuration and Storage Device User Guide, UG438 Software Manuals (iMPACT, PromGEN, and BitGen) Help  Software Manuals  Command Line Tool User Guide Platform Cable USB II Data Sheet, DS593 USB Cable Installation Guide, UG344 Troubleshooting BPI Programming Tutorial (evaluation kit page) Help  Xilinx on the Web  Support & Services  Products & Services  Boards and Kits  (select a board)  Documentation BPI programming tutorial for ML605 and SP601 demo boards

21. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2009 Xilinx, Inc. All Rights Reserved Where Can I Learn More? Check out the Configuration Problem Solver http://www.xilinx.com/support/troubleshoot.htm This utility provides a step-by-step debugging guide for all configuration schemes Xilinx Training www.xilinx.com/training Xilinx tools and architecture courses Hardware description language courses Basic FPGA architecture, Basic HDL Coding Techniques, and other Free training videos!

22. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2009 Xilinx, Inc. All Rights Reserved Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Trademark Information