2Objectives After completing this module, you will be able to: Explain some of the built in features that are already built into the ISE softwareUse the XST, MAP, and PAR options to manage power consumption
3Software Power Optimization Roadmap 2006XPE power estimatorXPower AnalyzerPower optimized routingISE8.2i2007XPE power estimatorXPowerPower optimized routingPower optimized synthesisPower optimized placerLUT power reduction (Virtex-5)New XPA GUI (EA)ISE9.1/2iISE10.1iEarly 2008XPE power estimatorXPower AnalyzerPower optimized routingPower optimized synthesisPower optimized placerLUT power reductionActivity based powerOptimizationPower optimized BRAM (sp3)ISE11.1iEarly 2009XPE power estimatorXPower AnalyzerPower optimized routingPower optimized synthesisPower optimized placerLUT power reductionActivity based power optimizationPower optimized BRAM BUFGCE automatic generationFF packing onto minimum clock leavesMore clock gating enhancementsMore synthesis enhancementsXilinx has a long history in power optimization software
4Power Optimizations in ISE Clock power reduction in placementFF packing onto Minimum Clock LeavesPower-aware LUT mappingClock gatingAutomatic use of the BUFGCE function in Virtex-4, Virtex-5, Spartan-3A/3ADSPNew clock gating features (BUFHCE)Power-aware synthesis (cluster high-activity nets in common slices)Minimizes net delayOlder power optimizations-lc auto (switch in MAP) allows splitting of LUT6 into two LUT5Reduce capacitance for non-timing critical netsMinimize wire lengths/capacitancePrevents duplication of logicReprogram LUT functions to reduce toggling nodesProduct ArchitectureDedicated Hard IPSW Power OptimizationProcess TechnologyLow Power Design TechniquesPower Estimation ToolsSW Power Optimization
5Design Goals & Strategies Right-click on Synthesize-XST and select Design Goals & StrategiesSets various options for XST, MAP, and PAR for power optimizationXST: Optimization Goal = AreaXST: Power Reduction = TrueMAP: Power Reduction = TruePAR: Power Reduction = True…and other optionsThese options are set in an XDS file (strategy file) that is user editable.
6Synthesis OptionsRight-click on Synthesize-XST Process Properties (default options shown)Optimization Goal – (Area)Reduces the overall amount of logic in the designThis will hurt speedPower Reduction – (when checked)XST optimizes the design to consume as little power as possible
7Other Synthesis Options Over-constraining (making timing constraints unnecessarily tight) during synthesis can significantly increase register useSeen as an average increase from 1–5 percentDo NOT over-constrain during synthesisGlobal optimization can lead to mixed resultsCan achieve ~10 percent flip-flop reductionGives back much of the utilization benefits (and sometimes more) due to control signal generationFSM optimizationTurning off FSM optimization can yield a small flip-flop savingsOne-hot encoding is not as usefulTry turning the Logic Replication synthesis option offThis is normally used to reduce net delays of high-fanout nets
8MAP OptionsRight-click on Map Process Properties (default options shown)Power Reduction – (when checked)Enables timing driven packing to minimize routingPower Activity File – (when Power Reduction is checked)Allows you to specify a VCD or SAIF file to guide mapThis file is an output from simulationAllows MAP to set frequencies and activity rates for internal signals
9PAR OptionsRight-click on Place & Route Process Properties (default options shown)Power Reduction – (when checked)Optimizes routing to enable power reductionPower Activity File – (when Power Reduction is checked)Allows you to specify a VCD or SAIF file to guide mapThis file is an output from simulationAllows PAR to set frequencies and activity rates for internal signalsSynthesis tools react to timing constraints by replicating and making designs bigger, which is how they improve performance.
10Power Optimization in ISE ISE v11.1 test results on a customer design (Virtex-5 LX110T)9% average Predicted Power Reduction18% dynamic power reduction for Vccint13% Static and Dynamic Power for VccintCustomer Measured Board-Level Power Results~ 13% Total Power Reduction
11SummarySetting the Design Goals & Strategies option to Power Optimization makes all the necessary setting your needXST and the ISE software contain numerous options that WILL reduce your design’s power consumptionAs new optimizations are built into the software, this will continue to be the best way to enable power optimizationAssociate a Power Activity File to enable the tools to optimize your system’s dynamic power consumptionPower optimization settings may hurt your design speedAlways use timing constraint to allow the tools to improve your system timing
12Where Can I Learn More?Xilinx Software Manuals (online or from ISE Help)Command Line User GuideExplains Power Optimization settings for Map and PARXST User GuideExplains Power Optimization settings
13Where Can I Learn More?Xilinx Education Services coursesDesigning with Spartan-6 and Virtex-6 Device Families courseHow to get the most out of both device familiesHow to build the best HDL code for your FPGA designHow to optimize your design for Spartan-6 and/or Virtex-6How to take advantage of the newest device featuresFree Video Based TrainingHow Do I Plan to Power My FPGA?Power EstimationWhat are the Spartan-6 Power Management Features?What are the Virtex-6 Power Management Features?What are FPGA Power Management HDL Coding Techniques?