Presentation on theme: "How to Convert a PLB-based Embedded System to an AXI-based System"— Presentation transcript:
1How to Convert a PLB-based Embedded System to an AXI-based System Xilinx Training
2Objectives After completing this module, you will be able to: Explain what the AXI protocol isIdentify the advantages of the AXI protocol over a shared bus modelList the various AXI-based system architectural models
3AXI is Part of AMBA AXI AMBA APB AHB Advanced Microcontroller Bus ArchitectureAMBAAPBAHBAXIAXI is a product of ARM, a company that designs and markets processor and peripheral IP to silicon vendors.Over the years, ARM has introduced various releases of its AMBA protocol interface to describe interconnect between the processor core and peripherals.For the most part, this protocol has been abstracted away from the user, as it has been buried in the single chip micro silicon that designers did not have, or need, access to. Now, the FPGA enables peripheral designers to build with this interface standard.Performance
4The ARM AXIIs an interface and protocol definition and is not a bus standardPreproduction in the EDK 12.3 releaseCurrently, only targets the MicroBlaze soft processor coreOnly for Spartan-6 and Virtex-6 devicesMost EDK peripherals will support AXI with the EDK 13.1 releaseWho should migrate their design?Anyone that believes the features are beneficial (AXI advantages are coming up)Anyone building an embedded design that will target the next generation of product families (after Spartan-6 and Virtex-6)Most embedded interconnect protocols define the implementation of the interconnect between the processor sub-system components.In AXI, only the signal names and operational protocol is defined. How the interconnect works is defined and optimized by the EDK software. This saves users from having to understand the details of the protocol.
5Pre-Production AXIISE Design Suite 12.3 is a pre-production release for designs that use AXI IPThe AXI IP peripherals in this release have not yet completed qualification for use in production designsSome wizard functionality in Xilinx Platform Studio does not yet fully support AXI-based designsFor ISE Design Suite 12.3, pre-production status applies only to designs making use of AXI IP peripheralsIf you design does not use these peripherals then your ok
6AXI is an Interface Specification PLB46“Shared Access” BusProcessorInterconnectPLBAXI SlavesAXI MastersAXIAXIAXIAXIPeripheralsAXI Interconnect IPImplementation is not described in the specSeveral companies build and sell “AXI interconnect IP”Xilinx is building its ownPLBBecause AXI does not define the interconnect, it is possible that the interconnect could be specified as a shared bus. In such a case, AXI and PLBv46 implementations would share some common operational properties.AXIAXIAXIAXIPLBAXIAXIPLBArrows indicate master/slave relationship, not direction of dataflowMasterSlaveAXI is an interface specification, not a bus specificationArbiter
7Why use AXI? Higher performance Easier to use Enable ecosystem AXI allows systems to be optimized for highest Fmax, maximum throughput, lower latency or some combination of those attributes. This flexibility enables you to build the most optimized products for your marketsEasier to useBy consolidating a broad array of interfaces into AXI, you only need to know one family of interfaces, regardless of whether they are embedded, DSP or logic users. This makes it easier to integrate IP from different domains, as well as developing your own IPEnable ecosystemPartners are embracing the move to AXI: an open, widely adopted interface standard. Many of them are already creating IP targeting AXI and other AMBA® interfaces. This gives you a greater catalog of IP, ultimately leading to faster time to marketOne of the goals of the Xilinx implementation of AXI is a unified interface protocol of Xilinx components. There will be a migration towards AXI in all facets of Xilinx technology and components. This will allow you the flexibility to rapidly define and interconnect standard and custom components, thus reducing the learning curve to use various technologies.
8Enhancements for FPGAs AXI is Part of AMBAAMBAAPBAHBAXIAXI-4Memory MapStreamLiteATBAMBA 3.0(2003)AMBA 4.0(Just Announced)Same SpecEnhancements for FPGAsAMBA = Advanced Microcontroller Bus ArchitectureRecently ARM announced the AXI4 spec. It is similar to AXI with three sub-interfaces to better target system specifications for performance and fabric usage.Memory Map: The traditional AXI3 address/data/control line interface with improvements such as larger data burst length phase.Stream: Targeting streaming applications to the same address. The transaction address phase has been removed. The focus is on high-performance data streaming.Lite: A simple interface, reducing fabric requirements, targeting peripherals in address space that only require a single data phase.InterfaceFeaturesSimilar toMemory Map / FullTraditional Address/Data Burst(single address, multiple data)PLBv46, PCIStreamingData-Only, BurstLocal Link / DSP Interfaces / FIFO / FSLLiteTraditional Address/Data—No Burst(single address, single data)PLBv46-singleOPB
9Design Conversion Re-building the Embedded System is usually best This is NOT difficultAdding processors, busses, and IP is literally “drag-and-drop”Custom IP…has some challengesIf the IP was built with the IP Wizard, the IP can be migrated using templates provided in the following solution recordIf the IP cannot be altered to AXI, just add the AXI-to-PLB bridge componentThis is described in the Xilinx AXI Reference GuideIf the IP was built from scratch, refer to the “Memory Mapped IP Feature Adoption and Support,” in the Xilinx AXI Reference GuideNew IP should be built to the AXI protocol.
10Documentation Xilinx AXI Reference Guide, UG761 ARM specifications AXI Usage in Xilinx FPGAsIntroduce key concepts of the AXI protocolExplains what features of AXI Xilinx has adoptedPLB-to-AXI Migration GuideHandbook for existing embedded customersHow to create and import AXI IPHow to debug and verify designs using ChipScopeHow to convert PLB-based IP to AXIARM specificationsAMBA AXI Protocol Version 2.0AMBA 4 AXI4-Stream Protocol Version 1.0
11Summary AXI is a signal interface protocol, not a shared bus standard AXI offers higher performance, ease of use, and has the support of many partnersThe AXI protocol has three different configurationsMemory Map/Full for OPBv46 replacementStreaming for data streaming applicationsLite for simpler systemsThe Xilinx AXI Reference Guide, UG761 contains more details about the AXI protocol and explains how to migrate IP to AXI
12Where Can I Learn More?Xilinx Education Services coursesEmbedded Systems Development courseEDK tool trainingHow to build custom IPHow to build your system softwareAdvanced Features and Techniques of Embedded Systems Design courseHow to debug your software on your hardware system with ChipScopeHow to optimize the use of the available memory controllersHow to design a Flash memory-based system and boot load from an off-chip memoryHow to add an interrupt controller into your hardware and software systemEmbedded Systems Software Development courseSoftware development and debugging with SDKHow to profile your software and develop custom device drivers