2Objectives After completing this training, you will be able to: Use various methods to resolve your design’s routing congestionUse the PlanAhead software to optimize your design’s routingNot everyone will have a routing problem, it will vary by application.Xilinx continues to focus on fine tuning software algorithms to improve routing optimization.
3If you have Area Constraints… Consider removing Area Constraints, unless you are certain they will be helpfulHelpful Area Constraints only place logic near dedicated hardware or reserved I/O pins, onlyIf your design has a top-level floorplan, unnecessary Area Constraints, or constrains a large percentage of the device, they may need to be removedIn general the fewer the Area Constraints, the betterA top-level floorplan usually constraints the top-most hierarchical blocks in your design, which means that over 80% of the design is constrainedNote that if you eventually get the design to complete PAR, you might consider re-adding some Area Constraints and try implementing the design again
4SmartXplorerConsider running SmartXplorer with the –cr (congestion reduction strategy) option from the command lineNote that this may have a negative impact on meeting your timing constraintsIf any of these strategies do complete routing, it could indicate that the timing constraints are too tightRefer to Command Line Tools User Guide, UG628 for more information about the command line flow and options.
5Run Additional Cost Tables Run 10+ cost tables to determine how consistent the routing congestion isIf a cost table is found where the congestion is greatly reduced or does not exist, compare the Congestion Metric Map output (in the PlanAhead Tool) with a failing resultEvaluate the placement of the dedicated hardware (block RAM, DSP slice, and distributed RAM). If certain dedicated hardware is near routing congestion, place that dedicated hardware in the better placement.Refer to the Re-use Flow section of the Floorplanning Methodology Guide, UG633
6Evaluating Routing Congestion Import the design into the PlanAhead tool to analyze the vertical and horizontal routingReview the Analyzing Implementation Results and Displaying Design Metrics sections of the PlanAhead User Guide, UG632 for more detailsAfter loading the design into PlanAhead, right-click on the die view and select Metric Horizontal/Vertical routing congestion per CLBLook for “Hot-Spots”These are locations on the die where most of the vertical or horizontal routing is used up
7What to do with a “Hot Spot” Determine if the logic in each hot spot is part of the same hierarchy of your designIf it isn’t use Area Constraints to separate the hierarchiesDon’t allow overlapping Area ConstraintsTry not to place timing critical logic poorlyEvaluate the primitives associated with the hot-spotsFor example, if the logic is distributed RAM driving DSP slice or block RAM, evaluate the placement of these resources
8What to do with a “Hot Spot” Evaluate the routing associated with hot-spotsIf they are high fanout nets…Evaluate the placement of the loads. If they are far apart, consider grouping the logic with an Area Constraint.Also consider replicating the source to reduce the fanoutDetermine if routing congestion is near the configuration and system monitor resourcesIf so, use the environment variableUAP_DENSMAP_CFG_NEIGHBORHOOD_SLOPE=1
9What to do with a “Hot Spot” Evaluate the pinout and GT placement in the PlanAhead tool to see if it is causing logic to spread outIf they are consider removing the offending pin assignments to see if this is the cause
10Evaluate Your Use of Control Signals High fanout control signalsDetermine if the signals that have a fanout > 1000 are resets or clock enablesReview the Spartan-6 and Virtex-6 HDL Coding Techniques Videos to determine if your design needs these signalsNever code a reset for simulation purposesAlso review the Retargeting Guidelines for Virtex-5 FPGAs, WP248 to determine if your design needs these signals
11Evaluate RAM Distribution Evaluate your use of Block RAM and Distributed RAM utilizationFrom the MAP report determine if distributed RAM is > 40% or if your use of Block RAM is < 60%Don’t waste block RAMIf your Block RAM usage is high evaluate the connectivity to these resources and consider floorplanning your memoriesFind all block RAMs with a common connectivity and group them into a single clock regionDo the same with distributed RAMsRe-implement and re-evaluate your critical timing paths
12Evaluate Your Clock Topology Use your synthesis schematic viewer or the PlanAhead Tool to evaluate your design’s usage of the clocking resourcesLook if any clocking components can be reducedBy reducing the number of BUFGs/BUFRs in a design, more flexibility is provided to the implementation toolsLook for gated clocks in the design and/or clocks that might be routed on local routing resourcesGated clocks can be re-targeted to the CE functionality of the BUFHCE to save routing resources
13Evaluate Your Clock Topology with PlanAhead Use the Find command (from PlanAhead) to trace your clocking resources or look for the primitive names
14Manage Your Device Utilization There is less flexibility in how the design gets implemented when the device utilization is high (usually over 80%)Avoid asynchronous resetsThey prevent logic from being merged into the block RAM and DSP slice resourcesSRLs cannot be inferred with any reset behaviorDisable KEEP HIERARCHY options and/or attributes during synthesis to ensure all possible optimizations can be done by your synthesis tool
15SummaryUse a minimal amount of Area Constraints until you are certain they are not creating routing congestionDon’t let logic from different hierarchical blocks be placed in regions where routing congestion is present (separate the logic)Consider running SmartXplorer with the –crAlso consider running the tools for multiple cost tablesEvaluate your routing congestion with the PlanAhead softwareFind your “Hot-Spots”Evaluate your use of control signals, memory resources, and clocking resourcesManage your device utilization
16Where Can I Learn More? Xilinx online documents Virtex-6 FPGA Routing Optimization Design Techniques, WP381Synthesis tool options, Implementation tool options, etc.PlanAhead User Guide, UG632Display design metricsFloorplanning Methodology Guide, UG633How to re-use placement information (Re-use Flow)Retargeting Guidelines for Virtex-5 FPGAs, WP248Helpful resource to clarify HDL coding techniquesCommand Line Tool User Guide, UG628How to run SmartXplorer with congestion reduction strategies
17Where Can I Learn More?Xilinx Education Services coursesDesigning with Spartan-6 and Virtex-6 Device Families courseHow to get the most out of both device familiesHow to build the best HDL code for your FPGA designHow to optimize your design for Spartan-6 and/or Virtex-6How to take advantage of the newest device featuresFree Video Based TrainingHow To Create Area Constraints with PlanAheadWhat are the Benefits of PlanAhead?What Design Techniques Help Avoid Routing Congestion?