Presentation on theme: "What Design Techniques Help Avoid Routing Congestion? Xilinx Training."— Presentation transcript:
What Design Techniques Help Avoid Routing Congestion? Xilinx Training
After completing this module, you will be able to: Explain the causes of routing congestion problems Use design techniques that optimize routing before a routing congestion problem develops Objectives
There is an increasing need for higher bandwidth and increased device utilization in Virtex-6 applications –Many applications require large amounts of data to be buffered to support high bandwidths generated by the SerDes features –This can create routing challenges and congestion that can impact timing closure –Not every design will be impacted, but it is better to build a better design sooner, rather than later Virtex-6 has three types of local routing resources –Single, double, and quad which connect to one, two, and four CLBs away –They have been optimized for performance and power Designs with a high number of control signals or high-fanout nets make routing more difficult Higher Bandwidth Applications
The design fails to route with NO warnings in PAR that detail specific nets that could not be routed PAR issues this warning… PAR Warning #464 The router has detected very dense, congested design. It is extremely unlikely the router will be able to finish the design and meet your timing requirements. To prevent excessive run time the router will change strategy. The router will now work to completely route this design but not to improve timing. This behavior will allow you to use the Static Timing Report and FPGA Editor to isolate the paths with timing problems. The cause of this behavior is either overly difficult constraints, or issue with the implementation of synthesis of logic in the critical timing path. If you are willing to accept a long run time, set the option “-xe c” to override the present behavior. Routing Congestion Symptoms
Another symptom is a series of “intermediate status” stages reported by PAR intermediate status: unrouted: Real time: 3 hrs 11 mins 59 secs intermediate status: unrouted: Real time: 3 hrs 41 mins 51 secs intermediate status: unrouted: Real time: 4 hrs 11 mins 47 secs intermediate status: unrouted: Real time: 4 hrs 11 mins 44 secs Routing Congestion Symptoms
Routing can be considered one of the most valuable resources Secondary Control Signals compete for the same resources as the rest of the active signals of the design Including timing-critical paths More available routing gives the tools a better chance to meet your timing objectives Tip: Using the GSR saves routing resources Reduce Sets, Resets, and CEs
The GSR input is an active-high global set/reset net that is active at the end of configuration –It uses a dedicated routing resource for signal distribution Saves general interconnect –It can also be used to restore the initial state of the FFs in the FPGA at any time (although not recommended) The initial state is communicated with an INIT attribute It drives the output FFs for each block RAM, but does not affect the contents of each memory or SRL Its routing delay is NOT characterized –It is connected to all synchronous elements through a wired OR gate This allows a local reset to also drive the FF’s set/reset port Global Reset Net
Some designs can get away without any resets but many designs need some resets –Very few designs require resets on all registers, but most designers want a global reset after initialization Most ASIC emulation also requires a described reset on every register. Implement this global reset with the built-in Global Set/Reset (GSR) GSR is good for initializing the values of your synchronous elements (FFs, Block RAMs) Delay of GSR is slow (3 clock cycles after configuration) so use it after configuration, but don’t reset again unless you can tolerate the entire design being reset Getting By
If you have a reset, you can initialize all registers in VHDL / Verilog code SR will cause the flip-flop to be set to the state inferred here –Inference is supported only for data types std_logic, bit_vector, bit, but NOT integer This is helpful for RTL simulation of the design –If it functions during simulation, it should function on the FPGA –Note…if you design without a reset in your design, you still get a free global reset VHDL: signal my_regsiter : std_logic_vector (7 downto 0) := (others <= ‘0’); Verilog: reg [7:0] my_register = 8’h00; Inferring an Initialization (XST only)
DCMs are a limited resource Using fewer DCMs saves global clock buffers DCM or PLL Logic and Flip-flops Case A – Embedded DCM In-1 In-x In-1 In-x Case B – External DCM DCM Pulling buried DCMs or PLLs up to the top level reduces the resources the clocking resources your design will use Minimizing the Use of DCMs or PLLs
To gate entire clock domains for power reduction, use the clock-enabled global buffer resource BUGCE or the BUFHCE –For applications that only pause the clock on small areas of the design, use the clock enable pin of the FPGA register –This saves general routing resources Tip: This will save routing resources Page 11 Global Clock Enable
Designs with a high number of control signals or high-fanout nets make routing more difficult Pulling buried DCMs or PLLs up to the top level Use the GSR on power-up to reset your circuit into a known state –The GSR is used after configuration, every time –Don’t use it to reset the circuit during normal operation –Build your HDL code properly to infer an initialization value Use the built-in CE features of the BUFHCE and the BUFGCE Summary
Xilinx online documents –www.support.xilinx.com PlanAhead User Guide, UG632 Display design metrics Floorplanning Methodology Guide, UG633 How to re-use placement information (Re-use Flow) Retargeting Guidelines for Virtex-5 FPGAs, WP248 Helpful resource to clarify HDL coding techniques Command Line Tool User Guide, UG628 How to run SmartXplorer with congestion reduction strategies Where Can I Learn More?
Xilinx Education Services courses –Designing with Spartan-6 and Virtex-6 Device Families course How to get the most out of both device families How to build the best HDL code for your FPGA design How to optimize your design for Spartan-6 and/or Virtex-6 How to take advantage of the newest device features Free Video-based Training –How To Create Area Constraints with PlanAhead –What are the Benefits of PlanAhead? –How do I Resolve Routing Congestion? Where Can I Learn More?