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Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010 V DD GND Select mask (dark field & clear field) P-well mask (dark field) Note body contacts: p-well.

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Presentation on theme: "Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010 V DD GND Select mask (dark field & clear field) P-well mask (dark field) Note body contacts: p-well."— Presentation transcript:

1 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010 V DD GND Select mask (dark field & clear field) P-well mask (dark field) Note body contacts: p-well to GND n-substrate to V DD CMOS Inverter Layout PMOS W/L=9 /2 NMOS W/L=3 /2 Active (clear field) Gate (clear field) Contact (dark field) Metal (clear field)

2 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010 Visualizing Layouts and Cross-Sections with SIMPLer SIMPL is a CAD tool created by Prof. Neureuther’s group allows IC designers to visualize device cross-sections corresponding to a fabrication process and physical layout. A Berkeley undergraduate student, Harlan Hile, created a mini-version of SIMPL (called SIMPLer) for EE40. It’s a JAVA program -> can be run on any computer, as well as on a web server. A 3D version SIMPL-GL can be accessed at

3 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010

4 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010

5 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010

6 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010

7 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010

8 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010 Define active areas; etch Si trenches Fill trenches (deposit SiO 2 then CMP) Twin Well + STI CMOS Process Form wells (implantation + thermal anneal) Grow gate oxide Deposit poly-Si and pattern gate electrodes Implant source/drain and body-contact regions Activate dopants (thermal anneal) Deposit insulating layer (SiO 2 ); planarize (CMP) Open contact holes; deposit & pattern metal layer

9 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F D view of a CMOS inverter after contact etch.

10 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F Well Engineering P-tub N-tub Twin Tub

11 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F Twin Well CMOS Process Flow

12 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F C(x) x Conventional well (depth and profile controlled by diffusion drive-in) Retrograde well (depth and profile controlled by implantation energy and dose) Retrograde Well - formed by high energy (>200keV) implantation

13 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F )Very low thermal budget for well formation (no need for diffusion drive-in) 2) Retrograde Well is formed AFTER field oxidation  small lateral diffusion and localized high conc under FOX Conventional vs Retrograde Well

14 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F Example: Formation of Channel Stop and Retrograde Well in a single step Channel stop Retrograde well

15 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F Multiple Implants for Well Engineering

16 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010 N Cheung EE243 Sp2010 Lec 1 16 Channel Engineering Shallow Oxide Trench Isolation

17 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F Generic Silicon-on-Insulator (SOI) CMOS Process Flow

18 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F SOI Process Flow (continued)

19 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F Smallest feature printable by lithography SiO 2 CVD oxide n+ poly-Si gate Thermal gate oxide Oxide spacer Angled Implant n+ pocket Normal S/D implant TiSi 2 Self-Aligned Channel V-gate by Optical Lithography (SALVO) Process * Sub-50nm channels

20 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F or SALVO Process Flow Chang et al, IEDM 2000 See Homework Problem

21 Professor N Cheung, U.C. Berkeley Lecture 19EE143 F SUMMARY OF IC PROCESS INTEGRATION MODULE Self aligned techniques: channel stop, Source/Drain, LDD, SALICIDE How to read process flow descriptions and cross-sections Generic NMOS Process with LOCOS Generic CMOS Process with LOCOS and single well Modified Processes: Shallow Trench Isolation (STI), Twin Wells, Retrograde Well, SOI CMOS


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