Download presentation

Presentation is loading. Please wait.

Published byTy Livings Modified over 2 years ago

1
EE130/230A Discussion 12 Peng Zheng 1

2
Velocity Saturation Velocity saturation limits I Dsat in sub-micron MOSFETS Simple model: E sat is the electric field at velocity saturation: for sat for < sat Lecture 22, Slide 2EE130/230A Fall 2013

3
Drain Saturation Voltage, V Dsat If sat L >> V GS -V T then the MOSFET is considered “long-channel”. This condition can be satisfied when – L is large, or – V GS is close to V T Lecture 22, Slide 3EE130/230A Fall 2013 Current saturation is limited by 2 mechanisms: 1.Pinch-off 2.Velocity saturation

4
Example: Drain Saturation Voltage Question: For V GS = 1.8 V, find V Dsat for an NMOSFET with T oxe = 3 nm, V T = 0.25 V, and W T = 45 nm, if L = (a) 10 m, (b) 1 m, (c) 0.1 m (d) 0.05 m Solution: From V GS, V T and T oxe, eff is 200 cm 2 V -1 s -1. E sat = 2v sat / eff = 8 10 4 V/cm m = 1 + 3T oxe /W T = 1.2 Lecture 22, Slide 4EE130/230A Fall 2013

5
(a) L = 10 m: V Dsat = (1/1.3V + 1/80V) -1 = 1.3 V (b) L = 1 m: V Dsat = (1/1.3V + 1/8V) -1 = 1.1 V (c) L = 0.1 m: V Dsat = (1/1.3V + 1/.8V) -1 = 0.5 V (d) L = 0.05 m: V Dsat = (1/1.3V + 1/.4V) -1 = 0.3 V Lecture 22, Slide 5EE130/230A Fall 2013

6
MOSFET I-V with Velocity Saturation In the linear region: Lecture 22, Slide 6EE130/230A Fall 2013

7
I Dsat with Velocity Saturation Substituting V Dsat for V DS in the linear-region I D equation gives For very short L: I Dsat is proportional to V GS –V T rather than (V GS – V T ) 2 I Dsat is not dependent on L Lecture 22, Slide 7EE130/230A Fall 2013

8
Short- vs. Long-Channel NMOSFET Short-channel NMOSFET: I Dsat is proportional to V GS -V Tn rather than (V GS -V Tn ) 2 V Dsat is lower than for long-channel MOSFET Channel-length modulation is apparent Lecture 22, Slide 8EE130/230A Fall 2013 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 6-23

9
The Short Channel Effect (SCE) |V T | decreases with L – Effect is exacerbated by high values of |V DS | This effect is undesirable (i.e. we want to minimize it!) because circuit designers would like V T to be invariant with transistor dimensions and bias condition “V T roll-off” Lecture 22, Slide 9EE130/230A Fall 2013 R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.3

10
depletion charge supported by gate (simplified analysis) n+n+ n+n+ VGVG p depletion region Large L: SD Small L: DS Depletion charge supported by S/D The smaller L is, the greater the percentage of depletion charge balanced by the S/D pn junctions: rjrj Lecture 22, Slide 10EE130/230A Fall 2013

11
V T Roll-Off: First-Order Model Minimize V T by reducing T oxe reducing r j increasing N A (trade-offs: degraded eff, m) MOSFET vertical dimensions should be scaled along with horizontal dimensions! Lecture 22, Slide 11EE130/230A Fall 2013 R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.4

12
Questions? 1. CMOS fabrication process / technology? 2. The MOSFET design project? 12 Good luck to Quiz#5!

Similar presentations

OK

Spring 2007EE130 Lecture 36, Slide 1 Lecture #36 ANNOUNCEMENTS Updated information for Term Project was posted on 4/14 Reminder: Coffee Hour today at ~4PM!

Spring 2007EE130 Lecture 36, Slide 1 Lecture #36 ANNOUNCEMENTS Updated information for Term Project was posted on 4/14 Reminder: Coffee Hour today at ~4PM!

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on magnets and electromagnets Ppt on political parties and electoral process in texas Ppt on atrial septal defect murmur Ppt on teachers day speech Ppt on basic leadership skills Ppt on regular expression validator Free ppt on festivals of india Ppt on the road not taken symbolism Laser video display ppt online Ppt on steve jobs biography